Ðþí  .Ä   8  +   (            ¬  *à                             "    amd,seattle-overdrive amd,seattle                                    +         3   7AMD Seattle (Rev.B0) Development Board (Overdrive)     interrupt-controller@e1101000             arm,gic-400 arm,cortex-a15-gic            =         R                        +         @   c    á             áð             á              á                   g      	           r            á                  y      v2m@e0080000              arm,gic-v2m-frame             �         c                       y            timer             arm,armv8-timer       0   g        ÿ        ÿ        ÿ      
  ÿ      smb           simple-bus                       +             r         �                          clk100mhz_0           fixed-clock          ›             ¨õá          ¸adl3clk_100mhz        clk375mhz             fixed-clock          ›             ¨ZÀ         ¸ccpclk_375mhz         clk333mhz             fixed-clock          ›             ¨Ù-@         ¸sataclk_333mhz           y         clk500mhz_0           fixed-clock          ›             ¨Íe          ¸pcieclk_500mhz        clk500mhz_1           fixed-clock          ›             ¨Íe          ¸dmaclk_500mhz         clk250mhz_4           fixed-clock          ›             ¨æ²€         ¸miscclk_250mhz           y         clk100mhz_1           fixed-clock          ›             ¨õá          ¸uartspiclk_100mhz            y         sata@e0300000             snps,dwc-ahci            c    à0                  g      c            Ë            Ò                    Ù      sata@e0d00000         	   ædisabled              snps,dwc-ahci            c    àÐ                  g      b            Ë            Ò                            Ù      iommu@e0200000            arm,mmu-401          c    à                   í            g      L         L                         Ù         y         iommu@e0c00000            arm,mmu-401          c    àÀ                  í            g      K         K                         Ù         y         i2c@e1000000             æok            snps,designware-i2c          c    á                   g      e            Ë         i2c@e0050000             æok            snps,designware-i2c          c    à                  g      T            Ë         serial@e1010000           arm,pl011 arm,primecell          c    á                  g      H            Ë              uartclk apb_pclk          spi@e1020000             æok            arm,pl022 arm,primecell          c    á                           g      J            Ë         	  apb_pclk          spi@e1030000             æok            arm,pl022 arm,primecell          c    á                           g      I            Ë         	  apb_pclk            (                        +       sdcard@0              mmc-spi-slot             c            /1-         A  €  H        P            `            p                        “             gpio@e1040000         	   ædisabled              arm,pl061 arm,primecell         §            c    á                  ³         g      g             =         R            Ë         	  apb_pclk          gpio@e1050000            æok            arm,pl061 arm,primecell         §            c    á                  ³          =         R            g      f            Ë         	  apb_pclk          gpio@e0020000         	   ædisabled              arm,pl061 arm,primecell         §            c    à                  ³          =         R            g      n            Ë         	  apb_pclk          gpio@e0030000         	   ædisabled              arm,pl061 arm,primecell         §            c    à                  ³          =         R            g      m            Ë         	  apb_pclk          gpio@e0080000            æok            arm,pl061 arm,primecell         §            c    à                  ³          =         R            g      i            Ë         	  apb_pclk          ccp@e0100000             æok            amd,ccp-seattle-v1a          c    à                  g                    Ù          Ò                   @      B        Ã         pcie@f0000000             pci-host-ecam-generic                        +            R           Ôpci         à               ê            c    ð                  õ  ÿ                 à                                                                    !                                  "                                  #                                  $                                  %                                  &                                  '                                  (                                  )                                  *                                  +             Ù         �C                                T   r               ïÿ                @       @       €                                                          æok        iommu@e0a00000            arm,mmu-401          c    à                   í            g      M         M                         Ù         y         ccn@e8000000              arm,ccn-504          c    è                   g      |         kcs@e0010000          	   ædisabled          	    ipmi-kcs            Ôipmi             c    à                  g      …                       )         clk250mhz_0           fixed-clock          ›             ¨æ²€         ¸xgmacclk0_dma_250mhz             y   	      clk250mhz_1           fixed-clock          ›             ¨æ²€         ¸xgmacclk0_ptp_250mhz             y   
      clk250mhz_2           fixed-clock          ›             ¨æ²€         ¸xgmacclk1_dma_250mhz             y         clk250mhz_3           fixed-clock          ›             ¨æ²€         ¸xgmacclk1_ptp_250mhz             y         xgmac@e0700000            amd,xgbe-seattle-v1a          P   c    àp             àx             á$            á%         `    á% ø             H   g      E         Z         [         \         ]         C            5        O            ]                  m                 �   
   
           ”                    ¦                 À                   Ú¡¢£¤¥           Ë   	   
        dma_clk ptp_clk         æxgmii            Ò                    Ù      xgmac@e0900000            amd,xgbe-seattle-v1a          P   c    à�             à˜             á$            á% €       `    á% ü             H   g      D         U         V         W         X         B            5        O            ]                  m                 �   
   
           ”                    ¦                 À                   Ú±²³´µ           Ë              dma_clk ptp_clk         æxgmii            Ò                    Ù      iommu@e0600000            arm,mmu-401          c    à`                  í            g      P         P                         Ù         y         iommu@e0800000            arm,mmu-401          c    à€                  í            g      O         O                         Ù         y            cpus                         +       cpu-map    cluster0       core0           ï         core1           ï            cluster1       core0           ï         core1           ï            cluster2       core0           ï         core1           ï            cluster3       core0           ï         core1           ï               cpu@0           Ôcpu           arm,cortex-a57           c            ópsci              À            @                    -  €         :   @        L           Y            y         cpu@1           Ôcpu           arm,cortex-a57           c           ópsci              À            @                    -  €         :   @        L           Y            y         cpu@100         Ôcpu           arm,cortex-a57           c           ópsci              À            @                    -  €         :   @        L           Y            y         cpu@101         Ôcpu           arm,cortex-a57           c          ópsci              À            @                    -  €         :   @        L           Y            y         cpu@200         Ôcpu           arm,cortex-a57           c           ópsci              À            @                    -  €         :   @        L           Y            y         cpu@201         Ôcpu           arm,cortex-a57           c          ópsci              À            @                    -  €         :   @        L           Y            y         cpu@300         Ôcpu           arm,cortex-a57           c           ópsci              À            @                    -  €         :   @        L           Y            y         cpu@301         Ôcpu           arm,cortex-a57           c          ópsci              À            @                    -  €         :   @        L           Y            y            l2-cache0                         @        "            b        p            y         l2-cache1                         @        "            b        p            y         l2-cache2                         @        "            b        p            y         l2-cache3                         @        "            b        p            y         l3-cache            �            €             @        "             b         y         pmu           arm,cortex-a57-pmu        `   g                           	          
                                                    �                              chosen           /smb/serial@e1010000          psci              arm,psci-0.2            úsmc          	compatible interrupt-parent #address-cells #size-cells model interrupt-controller #interrupt-cells reg interrupts ranges phandle msi-controller dma-ranges #clock-cells clock-frequency clock-output-names clocks iommus dma-coherent status #global-interrupts #iommu-cells clock-names spi-controller num-cs spi-max-frequency voltage-ranges pl022,hierarchy pl022,interface pl022,com-mode pl022,rx-level-trig pl022,tx-level-trig #gpio-cells gpio-controller amd,zlib-support device_type bus-range msi-parent interrupt-map-mask interrupt-map iommu-map reg-size reg-spacing amd,per-channel-interrupt amd,speed-set amd,serdes-blwc amd,serdes-cdr-rate amd,serdes-pq-skew amd,serdes-tx-amp amd,serdes-dfe-tap-config amd,serdes-dfe-tap-enable mac-address phy-mode cpu enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets l2-cache cache-unified next-level-cache cache-level interrupt-affinity stdout-path 