Ðþí  b¯   8  \ø   (            ·  \À                                                                      ,Freescale i.MX8DXL EVK           2fsl,imx8dxl-evk fsl,imx8dxl    aliases           =/bus@5b000000/ethernet@5b040000           G/bus@5b000000/ethernet@5b050000          Q/bus@5d000000/gpio@5d080000          W/bus@5d000000/gpio@5d090000          ]/bus@5d000000/gpio@5d0a0000          c/bus@5d000000/gpio@5d0b0000          i/bus@5d000000/gpio@5d0c0000          o/bus@5d000000/gpio@5d0d0000          u/bus@5d000000/gpio@5d0e0000          {/bus@5d000000/gpio@5d0f0000          �/bus@5d000000/mailbox@5d1c0000           …/bus@5a000000/i2c@5a820000           Š/bus@5b000000/mmc@5b010000           �/bus@5b000000/mmc@5b020000           ”/bus@5a000000/serial@5a060000         cpus                                 cpu@0            œcpu          2arm,cortex-a35           ¨                 ¬psci             º            Ë     û            Ò            á            õ         cpu@1            œcpu          2arm,cortex-a35           ¨                ¬psci             º            Ë     û            Ò            á            õ         l2-cache0            2cache            õ            opp-table            2operating-points-v2           ý         õ      opp-900000000               5¤é          B@         Ið      opp-1200000000              G†Œ          Èà         Ið         .         interrupt-controller@51a00000            2arm,gic-v3            ¨    Q              Q°                 :            K        `      	            õ         reserved-memory                                   k   dsp@92400000             ¨    ’@                  r         õ         linux,cma            2shared-dma-pool          y        ‚               ‡    ˜                   ”         pmu          2arm,armv8-pmuv3         `               psci             2arm,psci-1.0             ³smc       system-controller            2fsl,imx-scu         ¦tx0 rx0 gip3          $  ±                                 power-controller             2fsl,scu-pd          ¸         8  Ì       £   ë   ì   í   ä   å   æ   ç   î   ï   ð   ¦   ©         õ         clock-controller             2fsl,imx8dxl-clk fsl,scu-clk         ×            Ë              äxtal_32KHz xtal_24Mhz            õ         pinctrl          2fsl,imx8dxl-iomuxc          ðdefault         þ      hoggrp        0     <         I          @     L   k     L         õ         usbotg1grp                   !      usbotg2grp                   !      eqosgrp       ¨     -         ,         3         9         6         5         4         :         /         7         8         0         2         1               õ   .      fec1grp       À     #          *          -          ,          $       `   &       `   '       `   (       `   )       `   %       `          `          `           `   !       `   "       `          `         õ   (      lpspi3grp         0     =      @   >      @   ?      @   A      @      i2c2grp            s     !   t     !         õ         cm40lpuartgrp              S         R            i2c3grp            v     !   u     !      lpuart0grp             \          ]                õ         usdhc1grp         „     	      A   
       !          !          !          !          !          !          !          !          !          A         õ          usdhc2gpiogrp         $           @          !   !      !         õ   #      usdhc2grp         T     $     A   %      !   &      !   '      !   (      !   )      !         !         õ   "         ocotp            2fsl,imx8qxp-scu-ocotp                               mac@2c4          ¨  Ä            õ   *      mac@2c6          ¨  Æ            õ   0         rtc          2fsl,imx8qxp-sc-rtc        keys          "   2fsl,imx8qxp-sc-key fsl,imx-sc-key              t                watchdog             2fsl,imx-sc-wdt          .   <      thermal-sensor           2fsl,imx-sc-thermal          :            õ   	         timer            2arm,armv8-timer       0  `                                 
         thermal-zones      cpu-thermal0            P   ú        f  Ð        t   	  c   trips      trip0           „ ¡ø        �  Ð         £passive          õ   
      trip1           „ ð        �  Ð      	   £critical             cooling-maps       map0            ›   
            ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            pmic-thermal0           P   ú        f  Ð        t   	  ñ   trips      trip0           „ ­°        �  Ð         £passive          õ         trip1           „ èH        �  Ð      	   £critical             cooling-maps       map0            ›               ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ               clock-xtal32k            2fixed-clock         ×            ¯  €         ¿xtal_32KHz           õ         clock-xtal24m            2fixed-clock         ×            ¯n6         ¿xtal_24MHz           õ         bus@59000000             2simple-bus                                   kY       Y         clock-audio-ipg          2fixed-clock         ×            ¯	‰h         ¿audio_ipg_clk            õ         clock-controller@59580000            2fsl,imx8qxp-lpcg             ¨YX             ×            Ë                 Ò               4  ¿dsp_lpcg_adb_clk dsp_lpcg_ipg_clk dsp_lpcg_core_clk         à               õ         clock-controller@59590000            2fsl,imx8qxp-lpcg             ¨YY             ×            Ë           Ò           ¿dsp_ram_lpcg_ipg_clk            à              õ         dsp@596e8000             2fsl,imx8qxp-dsp          ¨Yn€  €          Ë                          äipg ocram core           à      â      ë                   ¦txdb0 txdb1 rxdb0 rxdb1       0  ±                                              î         	  üdisabled             bus@5a000000             2simple-bus                                   kZ       Z         clock-dma-ipg            2fixed-clock         ×            ¯	‰h         ¿dma_ipg_clk          õ         serial@5a060000          ¨Z             `       ä            Ë                   	  äipg baud                  9           Ä´         à      9        üokay          &   2fsl,imx8qxp-lpuart fsl,imx7ulp-lpuart           ðdefault         þ         serial@5a070000          ¨Z             `       å            Ë                   	  äipg baud                  :           Ä´         à      :      	  üdisabled          &   2fsl,imx8qxp-lpuart fsl,imx7ulp-lpuart         serial@5a080000          ¨Z             `       æ            Ë                   	  äipg baud                  ;           Ä´         à      ;      	  üdisabled          &   2fsl,imx8qxp-lpuart fsl,imx7ulp-lpuart         serial@5a090000          ¨Z	             `       ç            Ë                   	  äipg baud                  <           Ä´         à      <      	  üdisabled          &   2fsl,imx8qxp-lpuart fsl,imx7ulp-lpuart         clock-controller@5a460000            2fsl,imx8qxp-lpcg             ¨ZF             ×            Ë      9              Ò             '  ¿uart0_lpcg_baud_clk uart0_lpcg_ipg_clk          à      9         õ         clock-controller@5a470000            2fsl,imx8qxp-lpcg             ¨ZG             ×            Ë      :              Ò             '  ¿uart1_lpcg_baud_clk uart1_lpcg_ipg_clk          à      :         õ         clock-controller@5a480000            2fsl,imx8qxp-lpcg             ¨ZH             ×            Ë      ;              Ò             '  ¿uart2_lpcg_baud_clk uart2_lpcg_ipg_clk          à      ;         õ         clock-controller@5a490000            2fsl,imx8qxp-lpcg             ¨ZI             ×            Ë      <              Ò             '  ¿uart3_lpcg_baud_clk uart3_lpcg_ipg_clk          à      <         õ         i2c@5a800000             ¨Z€    @         `       Þ            Ë                     äper ipg               `           n6         à      `      	  üdisabled          6   2fsl,imx8dxl-lpi2c fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c         i2c@5a810000             ¨Z�    @         `       ß            Ë                     äper ipg               a           n6         à      a      	  üdisabled          6   2fsl,imx8dxl-lpi2c fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c         i2c@5a820000             ¨Z‚    @         `       à            Ë                     äper ipg               b           n6         à      b        üokay          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c                                   ¯ †         ðdefault         þ      gpio@20          2ti,tca6416           ¨             (        8            õ   +      gpio@21          2ti,tca6416           ¨   !         (        8            õ   :      i2c-mux@70           2nxp,pca9548                                    ¨   p   i2c@0                                      ¨       gpio@68          2maxim,max7322            ¨   h         (        8         	  üdisabled             õ   ;         i2c@4                                      ¨         i2c@5                                      ¨         i2c@6                                      ¨               i2c@5a830000             ¨Zƒ    @         `       á            Ë                     äper ipg               c           n6         à      c      	  üdisabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       clock-controller@5ac00000            2fsl,imx8qxp-lpcg             ¨ZÀ             ×            Ë      `              Ò                ¿i2c0_lpcg_clk i2c0_lpcg_ipg_clk         à      `         õ         clock-controller@5ac10000            2fsl,imx8qxp-lpcg             ¨ZÁ             ×            Ë      a              Ò                ¿i2c1_lpcg_clk i2c1_lpcg_ipg_clk         à      a         õ         clock-controller@5ac20000            2fsl,imx8qxp-lpcg             ¨ZÂ             ×            Ë      b              Ò                ¿i2c2_lpcg_clk i2c2_lpcg_ipg_clk         à      b         õ         clock-controller@5ac30000            2fsl,imx8qxp-lpcg             ¨ZÃ             ×            Ë      c              Ò                ¿i2c3_lpcg_clk i2c3_lpcg_ipg_clk         à      c         õ            bus@5b000000             2simple-bus                                   k[       [         clock-conn-axi           2fixed-clock         ×            ¯ÞCU        ¿conn_axi_clk             õ   3      clock-conn-ahb           2fixed-clock         ×            ¯	ï!ª        ¿conn_ahb_clk          clock-conn-ipg           2fixed-clock         ×            ¯÷�Õ        ¿conn_ipg_clk             õ   2      mmc@5b010000            `       Š            ¨[              Ë                           äipg ahb per         à      ø        üokay          $   2fsl,imx8dxl-usdhc fsl,imx8qxp-usdhc         ðdefault         þ            D            N         T         \      mmc@5b020000            `       ‹            ¨[              Ë   !      !      !            äipg ahb per         à      ù        j                      üokay          $   2fsl,imx8dxl-usdhc fsl,imx8qxp-usdhc         ðdefault         þ   "   #        D           �   $        ›   %              ¤   %              mmc@5b030000            `       Œ            ¨[              Ë   &      &      &            äipg ahb per         à      ú      	  üdisabled          $   2fsl,imx8dxl-usdhc fsl,imx8qxp-usdhc       ethernet@5b040000            ¨[           0  `                  ž          Ÿ          ¡             Ë   '      '      '      '            äipg ahb enet_clk_ref ptp                  û           sY@        ­           ¿           à      û      	  üdisabled             2fsl,imx8qm-fec          ðdefault         þ   (        Ñrgmii-txid          Ú   )         å        ö  Ð           *        mac-address    mdio                                 ethernet-phy@1           2ethernet-phy-ieee802.3-c22           ¨           (   +               4  '         D        Y   ,         õ   )   vddio-regulator         f w@        ~ w@         õ   ,               ethernet@5b050000            ¨[             `       £          ¢         (   Ë   -      -      -       -      -           ästmmaceth pclk ptp_ref tx mem                 ü           sY@        à      ü        üokay          (   2nxp,imx8dxl-dwmac-eqos snps,dwmac-5.10a                      –eth_wake_irq macirq         ðdefault         þ   .      	  Ñrgmii-id            Ú   /           0        mac-address    mdio             2snps,dwmac-mdio                              ethernet-phy@0           2ethernet-phy-ieee802.3-c22           ¨             ¦         D         ·        (   +              4           Ô @        Y   1         õ   /   vddio-regulator         f w@        ~ w@         õ   1               clock-controller@5b200000            2fsl,imx8qxp-lpcg             ¨[              ×            Ë      ø      2   3        Ò                9  ¿sdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk            à      ø         õ         clock-controller@5b210000            2fsl,imx8qxp-lpcg             ¨[!             ×            Ë      ù      2   3        Ò                9  ¿sdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk            à      ù         õ   !      clock-controller@5b220000            2fsl,imx8qxp-lpcg             ¨["             ×            Ë      ú      2   3        Ò                9  ¿sdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk            à      ú         õ   &      clock-controller@5b230000            2fsl,imx8qxp-lpcg             ¨[#             ×             Ë   4   4   3      û      2   2        Ò                         …  ¿enet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk            à      û         õ   '      clock-controller@5b240000            2fsl,imx8qxp-lpcg             ¨[$             ×            Ë   4   3   3      ü      2        Ò                      6  ¿eqos_ptp eqos_mem_clk eqos_aclk eqos_clk eqos_csr_clk           à      ü         õ   -      clock-conn-enet0-root            2fixed-clock         ×            ¯æ²€        ¿conn_enet0_root_clk          õ   4      usb@5b0e0000              2fsl,imx8dxl-usb fsl,imx7ulp-usb          ¨[                          `       ¦           æ   5        ñ   6             Ë   7        ý                       "           6           à           	  üdisabled       clock-dummy          2fixed-clock         ×            ¯          
  ¿clk_dummy            õ   7         usbmisc@5b0e0200            G            2fsl,imx7ulp-usbmisc          ¨[             õ   6      usbphy@0x5b110000         &   2fsl,imx8dxl-usbphy fsl,imx7ulp-usbphy            ¨[              Ë   8           à            	  üdisabled             õ   5      clock-controller@5b280000            2fsl,imx8qxp-lpcg             ¨[(             ×           Ò            Ë   2        ¿usboh3_2_phy_ipg_clk            à               õ   8         bus@5c000000             2simple-bus                                   k\       \         ddr-pmu@5c020000             2fsl,imx8-ddr-pmu             ¨\             `       G            bus@5d000000             2simple-bus                                   k]       ]         clock-lsio-mem           2fixed-clock         ×            ¯ëÂ         ¿lsio_mem_clk          clock-lsio-bus           2fixed-clock         ×            ¯õá         ¿lsio_bus_clk             õ   9      gpio@5d080000            ¨]             `       N            (        8            K        :           à      Ç          2fsl,imx8dxl-gpio fsl,imx35-gpio       gpio@5d090000            ¨]	             `       O            (        8            K        :           à      È          2fsl,imx8dxl-gpio fsl,imx35-gpio       gpio@5d0a0000            ¨]
             `       P            (        8            K        :           à      É          2fsl,imx8dxl-gpio fsl,imx35-gpio       gpio@5d0b0000            ¨]             `       Q            (        8            K        :           à      Ê          2fsl,imx8dxl-gpio fsl,imx35-gpio       gpio@5d0c0000            ¨]             `       R            (        8            K        :           à      Ë          2fsl,imx8dxl-gpio fsl,imx35-gpio         üokay             õ   <      gpio@5d0d0000            ¨]             `       S            (        8            K        :           à      Ì          2fsl,imx8dxl-gpio fsl,imx35-gpio         üokay             õ   %      gpio@5d0e0000            ¨]             `       T            (        8            K        :           à      Í          2fsl,imx8dxl-gpio fsl,imx35-gpio       gpio@5d0f0000            ¨]             `       U            (        8            K        :           à      Î          2fsl,imx8dxl-gpio fsl,imx35-gpio       mailbox@5d1b0000             ¨]             `       V           T         	  üdisabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1c0000             ¨]             `       W           T         -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu             õ         mailbox@5d1d0000             ¨]             `       X           T         	  üdisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1e0000             ¨]             `       Y           T         	  üdisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1f0000             ¨]             `       Z           T         	  üdisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d200000             ¨]              `       [           T           à      Ú      	  üdisabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d210000             ¨]!             `       ¹           T           à      Û      	  üdisabled          mailbox@5d280000             ¨](             `       À           T           à      â         õ         clock-controller@5d400000            2fsl,imx8qxp-lpcg             ¨]@             ×         4   Ë      ¿         ¿         ¿      9      ¿           Ò                      h  ¿pwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk         à      ¿      clock-controller@5d410000            2fsl,imx8qxp-lpcg             ¨]A             ×         4   Ë      À         À         À      9      À           Ò                      h  ¿pwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk         à      À      clock-controller@5d420000            2fsl,imx8qxp-lpcg             ¨]B             ×         4   Ë      Á         Á         Á      9      Á           Ò                      h  ¿pwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk         à      Á      clock-controller@5d430000            2fsl,imx8qxp-lpcg             ¨]C             ×         4   Ë      Â         Â         Â      9      Â           Ò                      h  ¿pwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk         à      Â      clock-controller@5d440000            2fsl,imx8qxp-lpcg             ¨]D             ×         4   Ë      Ã         Ã         Ã      9      Ã           Ò                      h  ¿pwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk         à      Ã      clock-controller@5d450000            2fsl,imx8qxp-lpcg             ¨]E             ×         4   Ë      Ä         Ä         Ä      9      Ä           Ò                      h  ¿pwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk         à      Ä      clock-controller@5d460000            2fsl,imx8qxp-lpcg             ¨]F             ×         4   Ë      Å         Å         Å      9      Å           Ò                      h  ¿pwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk         à      Å      clock-controller@5d470000            2fsl,imx8qxp-lpcg             ¨]G             ×         4   Ë      Æ         Æ         Æ      9      Æ           Ò                      h  ¿pwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk         à      Æ         chosen          `/bus@5a000000/serial@5a060000         memory@80000000          œmemory           ¨    €       @         regulator-0          2regulator-fixed         f 2Z         ~ 2Z         lmux3_en         {   :               €      regulator-1          2regulator-fixed         lfec1_supply         f 2Z         ~ 2Z         {   +               €      	  üdisabled          regulator-2          2regulator-fixed         lfec1_io_supply          f w@        ~ w@        {   ;                 ”         €      	  üdisabled          regulator-3          2regulator-fixed       	  lSD1_SPWR            f -ÆÀ        ~ -ÆÀ        {   <                ”        §  ˜         õ   $         	interrupt-parent #address-cells #size-cells model compatible ethernet0 ethernet1 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 mu1 i2c2 mmc0 mmc1 serial0 device_type reg enable-method next-level-cache clocks #cooling-cells operating-points-v2 phandle opp-shared opp-hz opp-microvolt clock-latency-ns opp-suspend #interrupt-cells interrupt-controller interrupts ranges no-map reusable size alloc-ranges linux,cma-default mbox-names mboxes #power-domain-cells wakeup-irq #clock-cells clock-names pinctrl-names pinctrl-0 fsl,pins linux,keycodes wakeup-source timeout-sec #thermal-sensor-cells polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device clock-frequency clock-output-names clock-indices power-domains memory-region status assigned-clocks assigned-clock-rates gpio-controller #gpio-cells bus-width no-sd no-sdio non-removable fsl,tuning-start-tap fsl,tuning-step vmmc-supply cd-gpios wp-gpios fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle fsl,magic-packet rx-internal-delay-ps nvmem-cells nvmem-cell-names reset-gpios reset-assert-us qca,disable-smarteee vddio-supply regulator-min-microvolt regulator-max-microvolt interrupt-names eee-broken-1000t qca,disable-hibernation-mode reset-deassert-us fsl,usbphy fsl,usbmisc ahb-burst-config tx-burst-size-dword rx-burst-size-dword #stream-id-cells #index-cells #mbox-cells stdout-path regulator-name gpio regulator-always-on enable-active-high off-on-delay-us 