Ðþí  sy   8  m¼   (            ½  m„                                                                   :   ,Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3         @   2toradex,colibri-imx8x-eval-v3 toradex,colibri-imx8x fsl,imx8qxp    aliases           =/bus@5b000000/ethernet@5b040000           G/bus@5b000000/ethernet@5b050000          Q/bus@5d000000/gpio@5d080000          W/bus@5d000000/gpio@5d090000          ]/bus@5d000000/gpio@5d0a0000          c/bus@5d000000/gpio@5d0b0000          i/bus@5d000000/gpio@5d0c0000          o/bus@5d000000/gpio@5d0d0000          u/bus@5d000000/gpio@5d0e0000          {/bus@5d000000/gpio@5d0f0000          �/bus@5a000000/i2c@5a800000           †/bus@5a000000/i2c@5a810000           ‹/bus@5a000000/i2c@5a820000           �/bus@5a000000/i2c@5a830000           •/bus@5b000000/mmc@5b010000           š/bus@5b000000/mmc@5b020000           Ÿ/bus@5b000000/mmc@5b030000           ¤/bus@5d000000/mailbox@5d1b0000           ¨/bus@5d000000/mailbox@5d1c0000           ¬/bus@5d000000/mailbox@5d1d0000           °/bus@5d000000/mailbox@5d1e0000           ´/bus@5d000000/mailbox@5d1f0000           ¸/bus@5a000000/serial@5a060000            À/bus@5a000000/serial@5a070000            È/bus@5a000000/serial@5a080000            Ð/bus@5a000000/serial@5a090000             Ø/vpu@2c000000/vpu-core@2d080000           â/vpu@2c000000/vpu-core@2d090000       "   ì/bus@5a000000/i2c@5a810000/rtc@68            ñ/system-controller/rtc        cpus                                 cpu@0            öcpu          2arm,cortex-a35                          psci              €         !   @        3           @  €         M   @        _   €        l           }     û           „           ˜           §         cpu@1            öcpu          2arm,cortex-a35                         psci              €         !   @        3           @  €         M   @        _   €        l           }     û           „           ˜           §         cpu@2            öcpu          2arm,cortex-a35                         psci              €         !   @        3           @  €         M   @        _   €        l           }     û           „           ˜           §         cpu@3            öcpu          2arm,cortex-a35                         psci              €         !   @        3           @  €         M   @        _   €        l           }     û           „           ˜           §         l2-cache0            2cache           ¯                      #   @        5           §            opp-table            2operating-points-v2          »        §      opp-900000000           Æ    5¤é         Í B@        Û Ið      opp-1200000000          Æ    G†Œ         Í Èà        Û Ið         ì         interrupt-controller@51a00000            2arm,gic-v3               Q              Q°                 ø            	              	           §         reserved-memory                                   )   decoder-boot@84000000               „                   0      encoder-boot@86000000               †                    0      decoder-rpc@92000000                ’                   0      dsp@92400000                ’@                  0        §         encoder-rpc@94400000                ”@       p           0         pmu          2arm,cortex-a35-pmu                         psci             2arm,psci-1.0            smc       system-controller            2fsl,imx-scu         7tx0 rx0 gip3          $  B                                 power-controller             2fsl,imx8qxp-scu-pd fsl,scu-pd           I           §         clock-controller             2fsl,imx8qxp-clk fsl,scu-clk         ]           §         pinctrl          2fsl,imx8qxp-iomuxc          jdefault         x            ad7879intgrp            ‚   ˜      !        §   &      adc0grp       0  ‚   d       `   c       `   h       `   g       `      canintgrp           ‚          @      csictlgrp           ‚   ¡          ¢             extio0grp           ‚   1     @        §         fec1grp       x  ‚   5          4          &       a   %     a   '       a   (       a   -       a   .       a   /       a   0      a        §   :      fec1slpgrp        x  ‚   5     A   4     A   &      A   %      A   '      A   (      A   -      A   .      A   /      A   0      A        §   ;      flexcan0grp         ‚   j       !   i       !      flexcan1grp         ‚   l       !   k       !      flexcan2grp         ‚   n       !   m       !      gpioblongrp         ‚   Ÿ      `      gpiokeysgrp         ‚   �   p A        §   A      hog0grp      8  ‚   *         �       a   ž          S          Š       a   ,         Ž       a   ¥          T          ‹       a   ¦          U          ˆ       a   R          ‰       a   §          ¨                                        ’          ©          X          ª          «          ¬               §         hog1grp         ‚   “          £               §         hogscfwgrp          ‚   �             i2c0grp         ‚   ›     !   š     !        §   $      i2c0mipilvds0grp            ‚   t    Æ      u    Æ         i2c0mipilvds1grp            ‚   x    Æ      y    Æ         i2c1grp         ‚   v     !   w     !        §   )      lcdifgrp         ,  ‚   L      `   H      `   K      `   J      `         `   7      `         `   8      `   9      `   :      `   ;      `   <      `   =      `   >      `   ?      `   @      `   A      `   B      `   C      `   E      `   F      `   G      `   I      `   )      `   P      `      lpspi2grp         0  ‚   Y      !   Z      @   [      @   \      @      lpuart0grp        0  ‚   o          p          i         j              §         lpuart2grp          ‚   r          q               §         lpuart3grp          ‚   m         n              §          lpuart3ctrlgrp        H  ‚   {          V          W          •                    ”               §   !      pciebgrp          $  ‚        a        a          `      pwmagrp         ‚   �       a   `      `      pwmbgrp         ‚   M      `      pwmcgrp         ‚   N      `      pwmdgrp         ‚   Œ       a   O      `      sai0grp       0  ‚   ^     @   a     @   ]     @   _     @      sgtl5000grp         ‚   ™      A      sgtl5000usbclkgrp           ‚   e      !        §   %      usb3503agrp         ‚   —      a      usbcdetgrp          ‚   3     @      usbh1reggrp         ‚        @      usdhc1grp         �  ‚   	      A   
       !          !          !          !          !          !          !          !          !          A          !        §   -      usdhc1-100mhzgrp          �  ‚   	      A   
       !          !          !          !          !          !          !          !          !          A          !        §   .      usdhc1-200mhzgrp          �  ‚   	      A   
       !          !          !          !          !          !          !          !          !          A          !        §   /      usdhc2gpiogrp           ‚   œ     !        §   3      usdhc2gpioslpgrp            ‚   œ      `        §   7      usdhc2grp         T  ‚         A          !           !   !       !   "       !   #       !          !        §   2      usdhc2-100mhzgrp          T  ‚         A          !           !   !       !   "       !   #       !          !        §   4      usdhc2-200mhzgrp          T  ‚         A          !           !   !       !   "       !   #       !          !        §   5      usdhc2slpgrp          T  ‚         `         `          `   !      `   "      `   #      `          !        §   6      wifigrp         ‚   ‡                ocotp            2fsl,imx8qxp-scu-ocotp                                  keys          "   2fsl,imx8qxp-sc-key fsl,imx-sc-key           ‹   t      	  šdisabled          rtc          2fsl,imx8qxp-sc-rtc        watchdog          "   2fsl,imx8qxp-sc-wdt fsl,imx-sc-wdt           ¡   <      thermal-sensor        *   2fsl,imx8qxp-sc-thermal fsl,imx-sc-thermal           ­           §   	         timer            2arm,armv8-timer       0                                   
         clock-xtal32k            2fixed-clock         ]            Ã  €         Óxtal_32KHz        clock-xtal24m            2fixed-clock         ]            Ãn6         Óxtal_24MHz        thermal-zones      cpu0-thermal            æ   ú        ü  Ð        
   	  c   trips      trip0            ¡ø        &  Ð         ýpassive         §   
      trip1            ð        &  Ð      	   ýcritical             cooling-maps       map0            1   
      0  6   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ               bus@58000000             2simple-bus                                   )X       X         clock-img-ipg            2fixed-clock         ]            ÃëÂ         Óimg_ipg_clk         §         jpegdec@58400000            X@           0        5         6         7         8           }                     Eper ipg         Q                     aëÂ ëÂ       (  v          �     ‚     ƒ     „         2nxp,imx8qxp-jpgdec        jpegenc@58450000            XE           0        1         2         3         4           }                     Eper ipg         Q                     aëÂ ëÂ       (  v          …     †     ‡     ˆ         2nxp,imx8qxp-jpgenc        clock-controller@585d0000            2fsl,imx8qxp-lpcg            X]             ]           }              „             0  Óimg_jpeg_dec_lpcg_clk img_jpeg_dec_lpcg_ipg_clk         v             §         clock-controller@585f0000            2fsl,imx8qxp-lpcg            X_             ]           }              „             0  Óimg_jpeg_enc_lpcg_clk img_jpeg_enc_lpcg_ipg_clk         v             §            vpu@2c000000                                     ),       ,                  ,                  v           	  šdisabled       mailbox@2d000000             2fsl,imx6sx-mu           -                    Õ           ’           v           	  šdisabled            §         mailbox@2d020000             2fsl,imx6sx-mu           -                   Ö           ’           v           	  šdisabled            §         vpu-core@2d080000           -              2nxp,imx8q-vpu-decoder           v             7tx0 tx1 rx        $  B                                     	  šdisabled          vpu-core@2d090000           -              2nxp,imx8q-vpu-encoder           v             7tx0 tx1 rx        $  B                                     	  šdisabled             bus@59000000             2simple-bus                                   )Y       Y         clock-audio-ipg          2fixed-clock         ]            Ã'         Óaudio_ipg_clk           §         clock-controller@59580000            2fsl,imx8qxp-lpcg            YX             ]           }                 „               4  Ódsp_lpcg_adb_clk dsp_lpcg_ipg_clk dsp_lpcg_core_clk         v              §         clock-controller@59590000            2fsl,imx8qxp-lpcg            YY             ]           }           „           Ódsp_ram_lpcg_ipg_clk            v             §         dsp@596e8000             2fsl,imx8qxp-dsp         Yn€  €         }                          Eipg ocram core           v      â      ë                   7txdb0 txdb1 rxdb0 rxdb1       0  B                                              ž         	  šdisabled             bus@5a000000             2simple-bus                                   )Z       Z         clock-dma-ipg            2fixed-clock         ]            Ã'         Ódma_ipg_clk         §   "      serial@5a060000         Z                    á           }                   	  Eipg baud            Q      9           aÄ´         v      9        šokay             2fsl,imx8qxp-lpuart          jdefault         x         serial@5a070000         Z                    â           }                   	  Eipg baud            Q      :           aÄ´         v      :      	  šdisabled             2fsl,imx8qxp-lpuart        serial@5a080000         Z                    ã           }                   	  Eipg baud            Q      ;           aÄ´         v      ;        šokay             2fsl,imx8qxp-lpuart          jdefault         x         serial@5a090000         Z	                    ä           }                   	  Eipg baud            Q      <           aÄ´         v      <        šokay             2fsl,imx8qxp-lpuart          jdefault         x       !      clock-controller@5a460000            2fsl,imx8qxp-lpcg            ZF             ]           }      9      "        „             '  Óuart0_lpcg_baud_clk uart0_lpcg_ipg_clk          v      9        §         clock-controller@5a470000            2fsl,imx8qxp-lpcg            ZG             ]           }      :      "        „             '  Óuart1_lpcg_baud_clk uart1_lpcg_ipg_clk          v      :        §         clock-controller@5a480000            2fsl,imx8qxp-lpcg            ZH             ]           }      ;      "        „             '  Óuart2_lpcg_baud_clk uart2_lpcg_ipg_clk          v      ;        §         clock-controller@5a490000            2fsl,imx8qxp-lpcg            ZI             ]           }      <      "        „             '  Óuart3_lpcg_baud_clk uart3_lpcg_ipg_clk          v      <        §         i2c@5a800000            Z€    @                Ü           }   #       #           Eper ipg         Q      `           an6         v      `        šokay          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c                                   Ã †         jdefault         x   $   %   touchscreen@2c           2adi,ad7879-1            jdefault         x   &           ,             '                      ¬           Å   x        Ü           ÷                      #           1ÿ            i2c@5a810000            Z�    @                Ý           }   (       (           Eper ipg         Q      a           an6         v      a        šokay          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c                                   Ã †         jdefault         x   )   rtc@68        	   2st,m41t0               h         i2c@5a820000            Z‚    @                Þ           }   *       *           Eper ipg         Q      b           an6         v      b      	  šdisabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       i2c@5a830000            Zƒ    @                ß           }   +       +           Eper ipg         Q      c           an6         v      c      	  šdisabled          $   2fsl,imx8qxp-lpi2c fsl,imx7ulp-lpi2c       clock-controller@5ac00000            2fsl,imx8qxp-lpcg            ZÀ             ]           }      `      "        „                Ói2c0_lpcg_clk i2c0_lpcg_ipg_clk         v      `        §   #      clock-controller@5ac10000            2fsl,imx8qxp-lpcg            ZÁ             ]           }      a      "        „                Ói2c1_lpcg_clk i2c1_lpcg_ipg_clk         v      a        §   (      clock-controller@5ac20000            2fsl,imx8qxp-lpcg            ZÂ             ]           }      b      "        „                Ói2c2_lpcg_clk i2c2_lpcg_ipg_clk         v      b        §   *      clock-controller@5ac30000            2fsl,imx8qxp-lpcg            ZÃ             ]           }      c      "        „                Ói2c3_lpcg_clk i2c3_lpcg_ipg_clk         v      c        §   +         bus@5b000000             2simple-bus                                   )[       [         clock-conn-axi           2fixed-clock         ]            ÃÞCU        Óconn_axi_clk            §   ?      clock-conn-ahb           2fixed-clock         ]            Ã	ï!ª        Óconn_ahb_clk          clock-conn-ipg           2fixed-clock         ]            Ã÷�Õ        Óconn_ipg_clk            §   >      mmc@5b010000                   è           [             }   ,      ,      ,            Eipg ahb per         v      ø        šokay          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc           I            S         a         g      "  jdefault state_100mhz state_200mhz           x   -        o   .        y   /      mmc@5b020000                   é           [             }   0      0      0            Eipg ahb per         v      ù        ƒ           ˜           šokay          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc           I           ¨   '   	           ±   1      (  jdefault state_100mhz state_200mhz sleep         x   2   3        o   4   3        y   5   3        ½   6   7         Ç      mmc@5b030000                   ê           [             }   8      8      8            Eipg ahb per         v      ú      	  šdisabled          "   2fsl,imx8qxp-usdhc fsl,imx7d-usdhc         ethernet@5b040000           [           0                                                }   9      9      9      9            Eipg ahb enet_clk_ref ptp            Q      û         û           aæ²€sY@        Ò           ä           v      û        šokay          .   2fsl,imx8qxp-fec fsl,imx8qm-fec fsl,imx6sx-fec           jdefault sleep           x   :        o   ;        örmii            ÿ   <         
   mdio                                 ethernet-phy@2           2ethernet-phy-ieee802.3-c22             d                   §   <            ethernet@5b050000           [           0                                               }   =      =      =      =            Eipg ahb enet_clk_ref ptp            Q      ü         ü           aæ²€sY@        Ò           ä           v      ü      	  šdisabled          .   2fsl,imx8qxp-fec fsl,imx8qm-fec fsl,imx6sx-fec         clock-controller@5b200000            2fsl,imx8qxp-lpcg            [              ]           }      ø      >   ?        „                9  Ósdhc0_lpcg_per_clk sdhc0_lpcg_ipg_clk sdhc0_lpcg_ahb_clk            v      ø        §   ,      clock-controller@5b210000            2fsl,imx8qxp-lpcg            [!             ]           }      ù      >   ?        „                9  Ósdhc1_lpcg_per_clk sdhc1_lpcg_ipg_clk sdhc1_lpcg_ahb_clk            v      ù        §   0      clock-controller@5b220000            2fsl,imx8qxp-lpcg            ["             ]           }      ú      >   ?        „                9  Ósdhc2_lpcg_per_clk sdhc2_lpcg_ipg_clk sdhc2_lpcg_ahb_clk            v      ú        §   8      clock-controller@5b230000            2fsl,imx8qxp-lpcg            [#             ]         0  }      û         û      ?      û      >   >        „                         …  Óenet0_lpcg_timer_clk enet0_lpcg_txc_sampling_clk enet0_lpcg_ahb_clk enet0_lpcg_rgmii_txc_clk enet0_lpcg_ipg_clk enet0_lpcg_ipg_s_clk            v      û        §   9      clock-controller@5b240000            2fsl,imx8qxp-lpcg            [$             ]         0  }      ü         ü      ?      ü      >   >        „                         …  Óenet1_lpcg_timer_clk enet1_lpcg_txc_sampling_clk enet1_lpcg_ahb_clk enet1_lpcg_rgmii_txc_clk enet1_lpcg_ipg_clk enet1_lpcg_ipg_s_clk            v      ü        §   =         bus@5c000000             2simple-bus                                   )\       \         ddr-pmu@5c020000             2fsl,imx8-ddr-pmu            \                    ƒ            bus@5d000000             2simple-bus                                   )]       ]         clock-lsio-mem           2fixed-clock         ]            ÃëÂ         Ólsio_mem_clk          clock-lsio-bus           2fixed-clock         ]            Ãõá         Ólsio_bus_clk            §   @      gpio@5d080000           ]                    ˆ            %        5            	        ø           v      Ç          2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d090000           ]	                    ‰            %        5            	        ø           v      È          2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0a0000           ]
                    Š            %        5            	        ø           v      É          2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0b0000           ]                    ‹            %        5            	        ø           v      Ê          2fsl,imx8qxp-gpio fsl,imx35-gpio         §   '      gpio@5d0c0000           ]                    Œ            %        5            	        ø           v      Ë          2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0d0000           ]                    �            %        5            	        ø           v      Ì          2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0e0000           ]                    Ž            %        5            	        ø           v      Í          2fsl,imx8qxp-gpio fsl,imx35-gpio       gpio@5d0f0000           ]                    �            %        5            	        ø           v      Î          2fsl,imx8qxp-gpio fsl,imx35-gpio       mailbox@5d1b0000            ]                    °           ’         	  šdisabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1c0000            ]                    ±           ’         -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu            §         mailbox@5d1d0000            ]                    ²           ’         	  šdisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1e0000            ]                    ³           ’         	  šdisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d1f0000            ]                    ´           ’         	  šdisabled          -   2fsl,imx8-mu-scu fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d200000            ]                     ¸           ’           v      Ú      	  šdisabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d210000            ]!                    ¹           ’           v      Û      	  šdisabled             2fsl,imx8qxp-mu fsl,imx6sx-mu          mailbox@5d280000            ](                    À           ’           v      â         2fsl,imx8qxp-mu fsl,imx6sx-mu            §         clock-controller@5d400000            2fsl,imx8qxp-lpcg            ]@             ]         4  }      ¿         ¿         ¿      @      ¿           „                      h  Ópwm0_lpcg_ipg_clk pwm0_lpcg_ipg_hf_clk pwm0_lpcg_ipg_s_clk pwm0_lpcg_ipg_slv_clk pwm0_lpcg_ipg_mstr_clk         v      ¿      clock-controller@5d410000            2fsl,imx8qxp-lpcg            ]A             ]         4  }      À         À         À      @      À           „                      h  Ópwm1_lpcg_ipg_clk pwm1_lpcg_ipg_hf_clk pwm1_lpcg_ipg_s_clk pwm1_lpcg_ipg_slv_clk pwm1_lpcg_ipg_mstr_clk         v      À      clock-controller@5d420000            2fsl,imx8qxp-lpcg            ]B             ]         4  }      Á         Á         Á      @      Á           „                      h  Ópwm2_lpcg_ipg_clk pwm2_lpcg_ipg_hf_clk pwm2_lpcg_ipg_s_clk pwm2_lpcg_ipg_slv_clk pwm2_lpcg_ipg_mstr_clk         v      Á      clock-controller@5d430000            2fsl,imx8qxp-lpcg            ]C             ]         4  }      Â         Â         Â      @      Â           „                      h  Ópwm3_lpcg_ipg_clk pwm3_lpcg_ipg_hf_clk pwm3_lpcg_ipg_s_clk pwm3_lpcg_ipg_slv_clk pwm3_lpcg_ipg_mstr_clk         v      Â      clock-controller@5d440000            2fsl,imx8qxp-lpcg            ]D             ]         4  }      Ã         Ã         Ã      @      Ã           „                      h  Ópwm4_lpcg_ipg_clk pwm4_lpcg_ipg_hf_clk pwm4_lpcg_ipg_s_clk pwm4_lpcg_ipg_slv_clk pwm4_lpcg_ipg_mstr_clk         v      Ã      clock-controller@5d450000            2fsl,imx8qxp-lpcg            ]E             ]         4  }      Ä         Ä         Ä      @      Ä           „                      h  Ópwm5_lpcg_ipg_clk pwm5_lpcg_ipg_hf_clk pwm5_lpcg_ipg_s_clk pwm5_lpcg_ipg_slv_clk pwm5_lpcg_ipg_mstr_clk         v      Ä      clock-controller@5d460000            2fsl,imx8qxp-lpcg            ]F             ]         4  }      Å         Å         Å      @      Å           „                      h  Ópwm6_lpcg_ipg_clk pwm6_lpcg_ipg_hf_clk pwm6_lpcg_ipg_s_clk pwm6_lpcg_ipg_slv_clk pwm6_lpcg_ipg_mstr_clk         v      Å      clock-controller@5d470000            2fsl,imx8qxp-lpcg            ]G             ]         4  }      Æ         Æ         Æ      @      Æ           „                      h  Ópwm7_lpcg_ipg_clk pwm7_lpcg_ipg_hf_clk pwm7_lpcg_ipg_s_clk pwm7_lpcg_ipg_slv_clk pwm7_lpcg_ipg_mstr_clk         v      Æ         chosen          A/bus@5a000000/serial@5a090000         regulator-module-3v3             2regulator-fixed         M+V3.3           \ 2Z         t 2Z         §   1      gpio-keys         
   2gpio-keys           jdefault         x   A   key-wakeup          ŒWake-Up         «   '   
            ’   �        �   
         ¯            	interrupt-parent #address-cells #size-cells model compatible ethernet0 ethernet1 gpio0 gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 gpio7 i2c0 i2c1 i2c2 i2c3 mmc0 mmc1 mmc2 mu0 mu1 mu2 mu3 mu4 serial0 serial1 serial2 serial3 vpu-core0 vpu-core1 rtc0 rtc1 device_type reg enable-method i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache clocks operating-points-v2 #cooling-cells phandle cache-level opp-shared opp-hz opp-microvolt clock-latency-ns opp-suspend #interrupt-cells interrupt-controller interrupts ranges no-map mbox-names mboxes #power-domain-cells #clock-cells pinctrl-names pinctrl-0 fsl,pins linux,keycodes status timeout-sec #thermal-sensor-cells clock-frequency clock-output-names polling-delay-passive polling-delay thermal-sensors temperature hysteresis trip cooling-device clock-names assigned-clocks assigned-clock-rates power-domains clock-indices #mbox-cells memory-region touchscreen-max-pressure adi,resistance-plate-x adi,first-conversion-delay adi,acquisition-time adi,median-filter-size adi,averaging adi,conversion-interval bus-width non-removable no-sd no-sdio pinctrl-1 pinctrl-2 fsl,tuning-start-tap fsl,tuning-step cd-gpios vmmc-supply pinctrl-3 disable-wp fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle fsl,magic-packet max-speed gpio-controller #gpio-cells stdout-path regulator-name regulator-min-microvolt regulator-max-microvolt label linux,code debounce-interval wakeup-source 