Ðþí  )N   8  &\   (            ò  &$                                                                      ,NXP i.MX8ULP EVK             2fsl,imx8ulp-evk fsl,imx8ulp    aliases       &   =/soc@0/bus@29800000/ethernet@29950000            G/soc@0/gpio@2e200080             M/soc@0/gpio@2d000080             S/soc@0/gpio@2d010080          !   Y/soc@0/bus@29800000/mmc@298d0000          !   ^/soc@0/bus@29800000/mmc@298e0000          !   c/soc@0/bus@29800000/mmc@298f0000          $   h/soc@0/bus@29000000/serial@29390000       $   p/soc@0/bus@29000000/serial@293a0000       $   x/soc@0/bus@29800000/serial@29860000       $   €/soc@0/bus@29800000/serial@29870000       cpus                                 cpu@0            ˆcpu          2arm,cortex-a35           ”                 ˜psci             ¦            ·         cpu@1            ˆcpu          2arm,cortex-a35           ”                ˜psci             ¦            ·         l2-cache0            2cache            ·            interrupt-controller@2d400000            2arm,gic-v3            ”    -@             -D                  ¿             Ð         å      	            ·         pmu          2arm,cortex-a35-pmu                        å                 ð            psci             2arm,psci-1.0             Ÿsmc       timer            2arm,armv8-timer       0   å                                 
         clock-frosc          2fixed-clock         q°         frosc           &          clock-lposc          2fixed-clock          B@        lposc           &          clock-rosc           2fixed-clock           €         rosc            &          clock-sosc           2fixed-clock         n6         sosc            &          sram@2201f000         
   2mmio-sram            ”    "ð                                         3        "ð       scmi-sram-section@0          2arm,scmi-shmem           ”                ·            firmware       scmi             2arm,scmi-smc            :Â  þ                                  E      protocol@11          ”           K            ·   
      protocol@15          ”           _               soc@0            2simple-bus                                   3            @      mailbox@27020000             2fsl,imx8ulp-mu-s4            ”'              å       O           u         bus@29000000             2simple-bus           ”)    €                                    3   mailbox@29220000             2fsl,imx8ulp-mu           ”)"              å       I           u         	  �disabled          mailbox@29230000             2fsl,imx8ulp-mu           ”)#              å       K           ˆ      .        u         	  �disabled          watchdog@292a0000             2fsl,imx8ulp-wdt fsl,imx7ulp-wdt          ”)*              å       L           ˆ               �               Ÿ              ¶   (      clock-controller@292c0000            2fsl,imx8ulp-cgc1             ”),             &            ·         clock-controller@292d0000            2fsl,imx8ulp-pcc3             ”)-             &           Â            ·         tpm@29340000              2fsl,imx8ulp-tpm fsl,imx7ulp-tpm          ”)4              å       W           ˆ                    Ïipg per       	  �disabled          i2c@29370000          $   2fsl,imx8ulp-lpi2c fsl,imx7ulp-lpi2c          ”)7              å       \           ˆ                    Ïper ipg         �              Ÿ      "        ÛÜl       	  �disabled          i2c@29380000          $   2fsl,imx8ulp-lpi2c fsl,imx7ulp-lpi2c          ”)8              å       ]           ˆ                    Ïper ipg         �              Ÿ      "        ÛÜl       	  �disabled          serial@29390000       &   2fsl,imx8ulp-lpuart fsl,imx7ulp-lpuart            ”)9              å       c           ˆ      	        Ïipg       	  �disabled          serial@293a0000       &   2fsl,imx8ulp-lpuart fsl,imx7ulp-lpuart            ”):              å       d           ˆ      
        Ïipg         �okay            ðdefault sleep           þ                    spi@293b0000                                        2fsl,imx8ulp-spi fsl,imx7ulp-spi          ”);              å       a           ˆ                    Ïper ipg         �              Ÿ      "        ÛÜl       	  �disabled          spi@293c0000                                        2fsl,imx8ulp-spi fsl,imx7ulp-spi          ”)<              å       b           ˆ                    Ïper ipg         �              Ÿ      "        ÛÜl       	  �disabled             bus@29800000             2simple-bus           ”)€   €                                    3   clock-controller@29800000            2fsl,imx8ulp-pcc4             ”)€             &           Â            ·   	      i2c@29840000          $   2fsl,imx8ulp-lpi2c fsl,imx7ulp-lpi2c          ”)„              å       ^           ˆ   	      	           Ïper ipg         �   	           Ÿ      "        ÛÜl       	  �disabled          i2c@29850000          $   2fsl,imx8ulp-lpi2c fsl,imx7ulp-lpi2c          ”)…              å       _           ˆ   	      	           Ïper ipg         �   	           Ÿ      "        ÛÜl       	  �disabled          serial@29860000       &   2fsl,imx8ulp-lpuart fsl,imx7ulp-lpuart            ”)†              å       e           ˆ   	           Ïipg       	  �disabled          serial@29870000       &   2fsl,imx8ulp-lpuart fsl,imx7ulp-lpuart            ”)‡              å       f           ˆ   	           Ïipg       	  �disabled          pinctrl@298c0000             2fsl,imx8ulp-iomuxc1          ”)Œ              ·      enetgrp       Ü     ¼       
       C   ¸  
ð   
      C   Ä     
      C   È  
ì   
      C    
ø   	      C   Ð  
ü   
      C   À       
       C   Ü       
       C   Ø       
       C   Ì  
ô   
      C  (  
Ð   	      C         ·         lpuart5grp        (    8  ð           <  ì                  ·         usdhc0grp         Ü                   C                B   (              C   $              C                  C                 C                 C                 C                 C                 C   ,             B         ·            mmc@298d0000          #   2fsl,imx8ulp-usdhc fsl,imx8mm-usdhc           ”)�              å       Ž           ˆ               	           Ïipg ahb per            
           )           >           N           �okay            ðdefault sleep           þ                       X      mmc@298e0000          #   2fsl,imx8ulp-usdhc fsl,imx8mm-usdhc           ”)Ž              å       �           ˆ               	           Ïipg ahb per            
           )           >           N         	  �disabled          mmc@298f0000          #   2fsl,imx8ulp-usdhc fsl,imx8mm-usdhc           ”)�              å       �           ˆ               	           Ïipg ahb per            
           )           >           N         	  �disabled          ethernet@29950000         -   2fsl,imx8ulp-fec fsl,imx6ul-fec fsl,imx6q-fec             ”)•              å       k           fint0            v           ˆ           �okay            ðdefault sleep           þ                      ˆ         	         7           Ïipg ahb ptp enet_clk_ref            �      7        Ÿ           šrmii            £      mdio                                 ethernet-phy@1           ”           ®            ·                  gpio@2d000080         "   2fsl,imx8ulp-gpio fsl,imx7ulp-gpio            ”-  €   -  @   @         ¾        Î            å       �             Ð         ¿           ˆ   	      	   	      
  Ïgpio port           Ú                    gpio@2d010080         "   2fsl,imx8ulp-gpio fsl,imx7ulp-gpio            ”- €   - @   @         ¾        Î            å       ƒ             Ð         ¿           ˆ   	      	   
      
  Ïgpio port           Ú          @          bus@2d800000             2simple-bus           ”-€   €                                    3   clock-controller@2da60000            2fsl,imx8ulp-cgc2             ”-¦             &         clock-controller@2da70000            2fsl,imx8ulp-pcc5             ”-§             &           Â            ·            gpio@2e200080         "   2fsl,imx8ulp-gpio fsl,imx7ulp-gpio            ”.  €   .  @   @         ¾        Î            å                    Ð         ¿           ˆ                  
  Ïgpio port           Ú                       chosen        $  æ/soc@0/bus@29000000/serial@293a0000       memory@80000000          ˆmemory           ”    €       €         clock-ext-rmii           2fixed-clock         úð€        ext_rmii_clk            &             ·         clock-ext-ts             2fixed-clock         úð€        ext_ts_clk          &             ·            	interrupt-parent #address-cells #size-cells model compatible ethernet0 gpio0 gpio1 gpio2 mmc0 mmc1 mmc2 serial0 serial1 serial2 serial3 device_type reg enable-method next-level-cache phandle #interrupt-cells interrupt-controller interrupts interrupt-affinity clock-frequency clock-output-names #clock-cells ranges arm,smc-id shmem #power-domain-cells #thermal-sensor-cells #mbox-cells status clocks assigned-clocks assigned-clock-parents timeout-sec #reset-cells clock-names assigned-clock-rates pinctrl-names pinctrl-0 pinctrl-1 fsl,pins power-domains fsl,tuning-start-tap fsl,tuning-step bus-width non-removable interrupt-names fsl,num-tx-queues fsl,num-rx-queues phy-mode phy-handle micrel,led-mode gpio-controller #gpio-cells gpio-ranges stdout-path 