Ðþí  "   8  Ð   (            R  ˜                                 openwrt,one mediatek,mt7981b                                     +            7OpenWrt One    cpus                         +       cpu@0             arm,cortex-a53           =             Acpu          Mpsci          cpu@1             arm,cortex-a53           =            Acpu          Mpsci             oscillator-40m            fixed-clock          [bZ          kclkxtal          ~          psci              arm,psci-1.0             Tsmc       soc           simple-bus            ‹                     +      interrupt-controller@c000000              arm,gic-v3            =                                                 ’      	             �         ²            Ã         clock-controller@10001000              mediatek,mt7981-infracfg syscon          =                      ~            Ã         clock-controller@1001b000              mediatek,mt7981-topckgen syscon          =    °                 ~            Ã         watchdog@1001c000             mediatek,mt7986-wdt          =    À                 ’       n            Ë            Ã         clock-controller@1001e000             mediatek,mt7981-apmixedsys           =    à                 ~         pwm@10048000              mediatek,mt7981-pwm          =    €              (   Ø                                       ßtop main pwm1 pwm2 pwm3          ë         serial@11002000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =                       ’       {            öuart wakeup          Ø                  	   ßbaud bus          	  disabled          serial@11003000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =     0                 ’       |            öuart wakeup          Ø                   	   ßbaud bus          	  disabled          serial@11004000       *    mediatek,mt7981-uart mediatek,mt6577-uart            =     @                 ’       }            öuart wakeup          Ø            !      	   ßbaud bus          	  disabled          i2c@11007000              mediatek,mt7981-i2c           =     p            !p€       €         ’       ˆ             Ø                  3      4         ßmain dma arb pmic                        +          	  disabled          spi@11009000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =     �                 ’       Ž             Ø            N      "      #          ßparent-clk sel-clk spi-clk hclk                      +          	  disabled          spi@1100a000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =                       ’       Œ             Ø            N      '      )          ßparent-clk sel-clk spi-clk hclk                      +          	  disabled          spi@1100b000          )    mediatek,mt7981-spi-ipm mediatek,spi-ipm             =     °                 ’       �             Ø            N      (      *          ßparent-clk sel-clk spi-clk hclk                      +          	  disabled          pinctrl@11d00000              mediatek,mt7981-pinctrl       �   =    Ð             À             Á             Ò             à             â             ð             ñ              °              I  gpio iocfg_rt iocfg_rm iocfg_rb iocfg_lb iocfg_bl iocfg_tm iocfg_tl eint              �         ’       á                                     9         #        3            ²            Ã         efuse@11f20000        %    mediatek,mt7981-efuse mediatek,efuse             =    ò                              +         clock-controller@15000000             mediatek,mt7981-ethsys syscon            =                       ~            Ë         wifi@18000000             mediatek,mt7981-wmac          0   =                   0            Ñ               0   ’       Õ          Ö          ×          Ø            Ø      _      \         ßmcu ap2conn         ?              Fconsys           timer             arm,armv8-timer                   0   ’                                 
         memory@40000000          =    @       @            Amemory           	compatible interrupt-parent #address-cells #size-cells model reg device_type enable-method clock-frequency clock-output-names #clock-cells ranges interrupts interrupt-controller #interrupt-cells phandle #reset-cells clocks clock-names #pwm-cells interrupt-names status reg-names gpio-ranges gpio-controller #gpio-cells resets reset-names 