Ðþí  ÿz   8  ò|   (            þ  òD                             t    google,spherion-rev3 google,spherion-rev2 google,spherion-rev1 google,spherion-rev0 google,spherion mediatek,mt8192                                  +            7Google Spherion (rev0 - 3)           =laptop     aliases          J/soc/ovl@14005000            O/soc/ovl@14006000            W/soc/ovl@14014000            _/soc/rdma@14007000           e/soc/rdma@14015000           k/soc/i2c@11f00000            p/soc/i2c@11d20000            u/soc/i2c@11d21000            z/soc/i2c@11cb0000            /soc/i2c@11d00000            „/soc/mmc@11f60000            ‰/soc/mmc@11f70000            Ž/soc/serial@11002000          fixed-factor-clock-13m            fixed-factor-clock           –             £            ª            ´            ¿clk13m           Ò   &      oscillator0           fixed-clock          –             ÚŒº€         ¿clk26m           Ò         oscillator1           fixed-clock          –             Ú  €          ¿clk32k        cpus                         +       cpu@0            êcpu           arm,cortex-a55           ö             úpsci             Úec3@                        €         %   @        7   €        D  €         Q   @        c   €        p           �               •  «        ¨            Ò   
      cpu@100          êcpu           arm,cortex-a55           ö            úpsci             Úec3@                        €         %   @        7   €        D  €         Q   @        c   €        p           �               •  «        ¨            Ò         cpu@200          êcpu           arm,cortex-a55           ö            úpsci             Úec3@                        €         %   @        7   €        D  €         Q   @        c   €        p           �               •  «        ¨            Ò         cpu@300          êcpu           arm,cortex-a55           ö            úpsci             Úec3@                        €         %   @        7   €        D  €         Q   @        c   €        p           �               •  «        ¨            Ò         cpu@400          êcpu           arm,cortex-a76           ö            úpsci             Ú�fÔÀ                                 %   @        7           D           Q   @        c           p   	        �              •           ¨            Ò         cpu@500          êcpu           arm,cortex-a76           ö            úpsci             Ú�fÔÀ                                 %   @        7           D           Q   @        c           p   	        �              •           ¨            Ò         cpu@600          êcpu           arm,cortex-a76           ö            úpsci             Ú�fÔÀ                                 %   @        7           D           Q   @        c           p   	        �              •           ¨            Ò         cpu@700          êcpu           arm,cortex-a76           ö            úpsci             Ú�fÔÀ                                 %   @        7           D           Q   @        c           p   	        �              •           ¨            Ò         cpu-map    cluster0       core0           ·   
      core1           ·         core2           ·         core3           ·         core4           ·         core5           ·         core6           ·         core7           ·               l2-cache0             cache           »                      '   @        9           p            Ç         Ò         l2-cache1             cache           »                      '   @        9           p            Ç         Ò   	      l3-cache              cache           »                       '   @        9            Ç         Ò         idle-states         Õpsci       cpu-retention-l           arm,idle-state          â           ù        
   7           Œ        +           Ò         cpu-retention-b           arm,idle-state          â           ù        
   #           ‘        +  Ð         Ò         cpu-off-l             arm,idle-state          â          ù        
   <           ›        +  \         Ò         cpu-off-b             arm,idle-state          â          ù        
   (           ›        +           Ò               pmu-a55           arm,cortex-a55-pmu                      <                  pmu-a76           arm,cortex-a76-pmu                      <                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  <                                             
                Ú Æ]@      opp-table-0           operating-points-v2          G         Ò   ]   opp-358000000           R    V¥€        Y 	@*      opp-399000000           R    ÈAÀ        Y 	pþ      opp-440000000           R    9Þ         Y 	¡Ò      opp-482000000           R    º¼€        Y 	Ò¦      opp-523000000           R    ,XÀ        Y 
z      opp-564000000           R    !�õ         Y 
4N      opp-605000000           R    $‘@        Y 
e"      opp-647000000           R    &�oÀ        Y 
•ö      opp-688000000           R    )         Y 
ÆÊ      opp-724000000           R    +']         Y       opp-748000000           R    ,•“         Y @Ü      opp-772000000           R    .É         Y q°      opp-795000000           R    /b¼À        Y ¢„      opp-819000000           R    0ÐòÀ        Y ÓX      opp-843000000           R    2?(À        Y ,      opp-866000000           R    3ž€        Y 5          soc                      +             simple-bus          g                                k   performance-controller@11bc10             mediatek,cpufreq-hw           ö     ¼            ½0               r            Ò         interrupt-controller@c000000              arm,gic-v3          Œ           �                        ´          ö                                    <      	                É         Ò      ppi-partitions     interrupt-partition-0           é   
                  Ò         interrupt-partition-1           é                     Ò               syscon@10000000            mediatek,mt8192-topckgen syscon          ö                       –            Ò         syscon@10001000            mediatek,mt8192-infracfg syscon          ö                      –           ò            Ò         syscon@10003000           mediatek,mt8192-pericfg syscon           ö     0                 –            Ò   3      pinctrl@10005000              mediatek,mt8192-pinctrl       °   ö     P            Â             Ñ             Ó             Ô             â             ç             ê             ò             ó              °              ]  ÿiocfg0 iocfg_rm iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_lb iocfg_rt iocfg_lt iocfg_tl eint             	                   %              Ü         ´        <       Ô               Œ        	€  1I2S_DP_LRCK IS_DP_BCLK I2S_DP_MCLK I2S_DP_DATAOUT SAR0_INT_ODL EC_AP_INT_ODL EDPBRDG_INT_ODL DPBRDG_INT_ODL DPBRDG_PWREN DPBRDG_RST_ODL I2S_HP_MCLK I2S_HP_BCK I2S_HP_LRCK I2S_HP_DATAIN AP_FLASH_WP_L TRACKPAD_INT_ODL EC_AP_HPD_OD SD_CD_ODL HP_INT_ODL_ALC EN_PP1000_DPBRDG AP_GPIO20 TOUCH_INT_L_1V8 UART_BT_WAKE_ODL AP_GPIO23 AP_SPI_FLASH_CS_L AP_SPI_FLASH_CLK EN_PP3300_DPBRDG_DX AP_SPI_FLASH_MOSI AP_SPI_FLASH_MISO I2S_HP_DATAOUT AP_GPIO30 I2S_SPKR_MCLK I2S_SPKR_BCLK I2S_SPKR_LRCK I2S_SPKR_DATAIN I2S_SPKR_DATAOUT AP_SPI_H1_TPM_CLK AP_SPI_H1_TPM_CS_L AP_SPI_H1_TPM_MISO AP_SPI_H1_TPM_MOSI BL_PWM EDPBRDG_PWREN EDPBRDG_RST_ODL EN_PP3300_HUB HUB_RST_L       SD_CLK SD_CMD SD_DATA3 SD_DATA0 SD_DATA2 SD_DATA1       PCIE_WAKE_ODL PCIE_RST_L PCIE_CLKREQ_ODL                        SPMI_SCL SPMI_SDA AP_GOOD UART_DBG_TX_AP_RX UART_AP_TX_DBG_RX UART_AP_TX_BT_RX UART_BT_TX_AP_RX MIPI_DPI_D0_R MIPI_DPI_D1_R MIPI_DPI_D2_R MIPI_DPI_D3_R MIPI_DPI_D4_R MIPI_DPI_D5_R MIPI_DPI_D6_R MIPI_DPI_D7_R MIPI_DPI_D8_R MIPI_DPI_D9_R MIPI_DPI_D10_R   MIPI_DPI_DE_R MIPI_DPI_D11_R MIPI_DPI_VSYNC_R MIPI_DPI_CLK_R MIPI_DPI_HSYNC_R PCM_BT_DATAIN PCM_BT_SYNC PCM_BT_DATAOUT PCM_BT_CLK AP_I2C_AUDIO_SCL AP_I2C_AUDIO_SDA SCP_I2C_SCL SCP_I2C_SDA AP_I2C_WLAN_SCL AP_I2C_WLAN_SDA AP_I2C_DPBRDG_SCL AP_I2C_DPBRDG_SDA EN_PP1800_DPBRDG_DX EN_PP3300_EDP_DX EN_PP1800_EDPBRDG_DX EN_PP1000_EDPBRDG SCP_JTAG0_TDO SCP_JTAG0_TDI SCP_JTAG0_TMS SCP_JTAG0_TCK SCP_JTAG0_TRSTN EN_PP3000_VMC_PMU EN_PP3300_DISPLAY_DX TOUCH_RST_L_1V8 TOUCH_REPORT_DISABLE   AP_I2C_TRACKPAD_SCL_1V8 AP_I2C_TRACKPAD_SDA_1V8 EN_PP3300_WLAN BT_KILL_L WIFI_KILL_L SET_VMC_VOLT_AT_1V8 EN_SPK AP_WARM_RST_REQ   EN_PP3000_SD_S3 AP_EDP_BKLTEN    AP_SPI_EC_CLK AP_SPI_EC_CS_L AP_SPI_EC_MISO AP_SPI_EC_MOSI AP_I2C_EDPBRDG_SCL AP_I2C_EDPBRDG_SDA MT6315_PROC_INT MT6315_GPU_INT UART_SERVO_TX_SCP_RX UART_SCP_TX_SERVO_RX BT_RTS_AP_CTS AP_RTS_BT_CTS UART_AP_WAKE_BT_ODL WLAN_ALERT_ODL EC_IN_RW_ODL H1_AP_INT_ODL            MSDC0_CMD MSDC0_DAT0 MSDC0_DAT2 MSDC0_DAT4 MSDC0_DAT6 MSDC0_DAT1 MSDC0_DAT5 MSDC0_DAT7 MSDC0_DSL MSDC0_CLK MSDC0_DAT3 MSDC0_RST_L SCP_VREQ_VAO AUD_DAT_MOSI2 AUD_NLE_MOSI1 AUD_NLE_MOSI0 AUD_DAT_MISO2 AP_I2C_SAR_SDA AP_I2C_SAR_SCL AP_I2C_PWR_SCL AP_I2C_PWR_SDA AP_I2C_TS_SCL_1V8 AP_I2C_TS_SDA_1V8 SRCLKENA0 SRCLKENA1 AP_EC_WATCHDOG_L PWRAP_SPI0_MI PWRAP_SPI0_CSN PWRAP_SPI0_MO PWRAP_SPI0_CK AP_RTC_CLK32K AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1          Ò      anx7625-default-pins             Ò   ?   pins-out            A  )   *          H      pins-in         A            S         `         aud-clk-mosi-off-pins            Ò   ‰   pins-mosi-off           A  Ö   ×          aud-clk-mosi-on-pins             Ò   Š   pins-mosi-on            A  Ö  ×        m   
         aud-dat-miso-ch34-off-pins           Ò   Ÿ   pins-miso-off           A  Ç          aud-dat-miso-ch34-on-pins            Ò       pins-miso-on            A  Ç         aud-dat-miso-off-pins            Ò   �   pins-miso-off           A  Ú   Û          aud-dat-miso-on-pins             Ò   Ž   pins-miso-on            A  Ú  Û        m   
         aud-dat-miso2-off-pins           Ò   •   pins-miso-off           A  Ç          aud-dat-miso2-on-pins            Ò   –   pins-miso-on            A  Ç         aud-dat-mosi-ch34-off-pins           Ò   �   pins-mosi-off           A  Ä          aud-dat-mosi-ch34-on-pins            Ò   ž   pins-mosi-on            A  Ä         aud-dat-mosi-off-pins            Ò   ‹   pins-mosi-off           A  Ø   Ù          aud-dat-mosi-on-pins             Ò   Œ   pins-mosi-on            A  Ø  Ù        m   
         aud-gpio-i2s3-off-pins           Ò   —   pins-i2s3-off           A      !   #          aud-gpio-i2s3-on-pins            Ò   ˜   pins-i2s3-on            A     !  #         aud-gpio-i2s8-off-pins           Ò   ™   pins-i2s8-off           A  
                   aud-gpio-i2s8-on-pins            Ò   š   pins-i2s8-on            A  
               aud-gpio-i2s9-off-pins           Ò   ›   pins-i2s9-off           A            aud-gpio-i2s9-on-pins            Ò   œ   pins-i2s9-on            A           aud-gpio-tdm-off-pins            Ò   ¡   pins-tdm-off            A                      aud-gpio-tdm-on-pins             Ò   ¢   pins-tdm-on         A                  aud-nle-mosi-off-pins            Ò   “   pins-nle-mosi-off           A  Å   Æ          aud-nle-mosi-on-pins             Ò   ”   pins-nle-mosi-on            A  Å  Æ         cr50-irq-default-pins            Ò   -   pins-gsc-ap-int-odl         A  «          S         cros-ec-irq-default-pins             Ò   +   pins-ec-ap-int-odl          A            S         `         i2c0-default-pins            Ò   R   pins-bus            A  Ì  Í        `   Ë        |  è         i2c1-default-pins            Ò   J   pins-bus            A  v  w        `   Ë        |  è         i2c2-default-pins            Ò   M   pins-bus            A  �  Ž        `   Ë         i2c3-default-pins            Ò   >   pins-bus            A     ¡         ”        |  è         i2c7-default-pins            Ò   H   pins-bus            A  |  }         ”        |  è         mmc0-default-pins            Ò   U   pins-cmd-dat          $  A  ¸  ¼  ¹  Á  º  ½  »  ¾  ·         S        m           `   e      pins-clk            A  À        m           ¡   f      pins-rst            A  Â        m           ¡   e         mmc0-uhs-pins            Ò   V   pins-cmd-dat          $  A  ¸  ¼  ¹  Á  º  ½  »  ¾  ·         S        m   
        `   e      pins-clk            A  À        m   
        ¡   f      pins-rst            A  Â        m           ¡   e      pins-ds         A  ¿        m   
        ¡   f         mmc1-default-pins            Ò   Y   pins-cmd-dat            A  6  8  7  5  4         S        m           `   e      pins-clk            A  3        m           ¡   f      pins-insert         A            S         `         mmc1-uhs-pins            Ò   Z   pins-cmd-dat            A  6  8  7  5  4         S        m           `   e      pins-clk            A  3         S        m           ¡   f         nor-flash-default-pins           Ò   <   pins-cs-io1         A             S         `        m   
      pins-io0            A           `        m   
      pins-clk            A           S         `        m   
         pcie-default-pins            Ò   :   pins-pcie-wake          A  ?         `      pins-pcie-pereset           A  @      pins-pcie-clkreq            A  A         `      pins-wifi-kill          A  ‘          °         pp1000-dpbrdg-en-pins            Ò      pins-en         A            H         pp1000-mipibrdg-en-pins          Ò   �   pins-en         A  �          H         pp1800-dpbrdg-en-pins            Ò   ‚   pins-en         A  ~          H         pp1800-mipibrd-en-pins           Ò   ƒ   pins-en         A  €          H         pp3300-dpbrdg-en-pins            Ò   „   pins-en         A            H         pp3300-mipibrdg-en-pins          Ò   …   pins-en         A            H         pp3300-wlan-pins             Ò   †   pins-pcie-en-pp3300-wlan            A  �          °         pwm0-default-pins            Ò   )   pins-pwm            A  (      pins-inhibit            A  ˜          °         rt1015p-default-pins             Ò   ‡   pins            A  “          H         scp-pins             Ò   /   pins-vreq-vao           A  Ã         spi1-default-pins            Ò   *   pins-cs-mosi-clk            A  �  Ÿ  œ         ”      pins-miso           A  ž         ¡         spi5-default-pins            Ò   ,   pins-bus            A  &  %   '  $         ”         trackpad-default-pins            Ò   N   pins-int-n          A            S        `   g         touchscreen-default-pins             Ò   S   pins-irq            A            S         `      pins-reset          A  ‰          °      pins-report-sw          A  Š          H         vow-clk-miso-off-pins            Ò   ‘   pins-miso-off           A  Û          vow-clk-miso-on-pins             Ò   ’   pins-miso-on            A  Û         vow-dat-miso-off-pins            Ò   �   pins-miso-off           A  Ú          vow-dat-miso-on-pins             Ò   �   pins-miso-on            A  Ú            syscon@10006000       )    mediatek,mt8192-scpsys syscon simple-mfd             ö     `           power-controller          !    mediatek,mt8192-power-controller                         +            ¼            Ò   7   power-domain@0           ö             £            :      /        Ðaudio audio1 audio2         Ü           ¼          power-domain@1           ö            £              Ðconn            Ü           ¼          power-domain@2           ö            £                    Ðmfg alt                      +            ¼           î      power-domain@3           ö           Ü                        +            ¼           î      power-domain@4           ö           ¼          power-domain@5           ö           ¼          power-domain@6           ö           ¼          power-domain@7           ö           ¼          power-domain@8           ö           ¼                power-domain@9           ö   	      (   £                                    !  Ðdisp disp-0 disp-1 disp-2 disp-3            Ü                        +            ¼      power-domain@10          ö   
      (   £                                       Ðipe ipe-0 ipe-1 ipe-2 ipe-3         Ü           ¼          power-domain@11          ö            £                           Ðisp isp-0 isp-1         Ü           ¼          power-domain@12          ö            £                           Ðisp2 isp2-0 isp2-1          Ü           ¼          power-domain@13          ö            £                  
  Ðmdp mdp-0           Ü           ¼          power-domain@14          ö            £      3              Ðvenc venc-0         Ü           ¼          power-domain@15          ö             £      4                              Ðvdec vdec-0 vdec-1 vdec-2           Ü                        +            ¼      power-domain@16          ö            £   !      !      !            Ðvdec2-0 vdec2-1 vdec2-2         ¼             power-domain@17          ö         (   £      
   "       "      "      "           Ðcam cam-0 cam-1 cam-2 cam-3         Ü                        +            ¼      power-domain@18          ö            £   #            Ðcam_rawa-0          ¼          power-domain@19          ö            £   $            Ðcam_rawb-0          ¼          power-domain@20          ö            £   %            Ðcam_rawc-0          ¼                      watchdog@10007000             mediatek,mt8192-wdt          ö     p                ò            Ò   6      syscon@1000c000       "    mediatek,mt8192-apmixedsys syscon            ö     À                 –            Ò   2      timer@10017000        ,    mediatek,mt8192-timer mediatek,mt6765-timer          ö    p                <       é                £   &      pwrap@10026000            mediatek,mt6873-pwrap            ö    `                ÿpwrap           <       Ü                £                   	  Ðspi wrap            ü                    ƒ   pmic              mediatek,mt6359          ´        Œ           #      Ö      adc           mediatek,mt6359-auxadc          7         mt6359codec         I           \           p         regulators            mediatek,mt6359-regulator      buck_vs1            „vs1         “ 5         « !‘À        Ã             ß      buck_vgpu11         „vgpu11          “ €        « 7        ó  ˆ        Ã   È                           ß      buck_vmodem         „vmodem          “ €        « Èà        ó  *        Ã   È      buck_vpu            „vpu         “ €        « 7        ó  ˆ        Ã   È                        buck_vcore          „vcore           “ €        « Ö         ó  ˆ        Ã   È                        buck_vs2            „vs2         “ 5         « j         Ã             ß         Ò   €      buck_vpa            „vpa         “ ¡         « 7±Ð        Ã  ,      buck_vproc2         „vproc2          “ €        « 7        ó  L        Ã   È                        buck_vproc1         „vproc1          “ €        « 7        ó  L        Ã   È                        buck_vcore_sshub            „vcore_sshub         “ €        « 7      buck_vgpu11_sshub           „vgpu11_sshub            “ Æ        « Æ         ß      ldo_vaud18          „vaud18          “ w@        « w@        Ã   ð      ldo_vsim1           „vsim1           “ ð         « /M`      ldo_vibr            „vibr            “ O€        « 2Z       ldo_vrf12           „vrf12           “ Èà        « Ö          ß      ldo_vusb            „vusb            “ -ÆÀ        « -ÆÀ        Ã  À         ß      ldo_vsram_proc2         „vsram_proc2         “ ¡         « ½¶        ó  L        Ã   ð         ß      ldo_vio18           „vio18           “ ð         « ýà        Ã  À         ß         Ò   K      ldo_vcamio          „vcamio          “ ð         « ýà      ldo_vcn18           „vcn18           “ w@        « w@        Ã   ð      ldo_vfe28           „vfe28           “ *¹€        « *¹€        Ã   x      ldo_vcn13           „vcn13           “ »         « Ö       ldo_vcn33_1_bt          „vcn33_1_bt          “ *¹€        « 5gà      ldo_vcn33_1_wifi            „vcn33_1_wifi            “ *¹€        « 5gà      ldo_vaux18          „vaux18          “ w@        « w@        Ã   ð         ß      ldo_vsram_others            „vsram_others            “ q°        « 5         ó  ˆ        Ã   ð                    7  '         Ò         ldo_vefuse          „vefuse          “ ð         « „€      ldo_vxo22           „vxo22           “ w@        « !‘À         ß      ldo_vrfck           „vrfck           “ ã`        « ð       ldo_vrfck_1         „vrfck           “ ëÀ        « j       ldo_vbif28          „vbif28          “ *¹€        « *¹€        Ã   ð      ldo_vio28           „vio28           “ *¹€        « 2Z          ß      ldo_vemc            „vemc            “ ,@         « 2Z       ldo_vemc_1          „vemc            “ &%         « 2Z          Ò   W      ldo_vcn33_2_bt          „vcn33_2_bt          “ *¹€        « 5gà      ldo_vcn33_2_wifi            „vcn33_2_wifi            “ *¹€        « 5gà      ldo_va12            „va12            “ O€        « Ö          ß      ldo_va09            „va09            “ 5         « O€      ldo_vrf18           „vrf18           “ ð         « žP      ldo_vsram_md          	  „vsram_md            “ ¡         « ½¶        ó  *        Ã   ð      ldo_vufs            „vufs            “ ð         « ýà         ß         Ò   X      ldo_vm18            „vm18            “ ð         « ýà         ß      ldo_vbbck           „vbbck           “ Èà        « O€      ldo_vsram_proc1         „vsram_proc1         “ ¡         « ½¶        ó  L        Ã   ð         ß      ldo_vsim2           „vsim2           “ ð         « /M`      ldo_vsram_others_sshub          „vsram_others_sshub          “ ¡         « ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt6873-spmi              ö    p            �                ÿpmif spmimst             £                   8      (  Ðpmif_sys_ck pmif_tmr_ck spmimst_clk_mux         ü                    ƒ                     +       pmic@6            mediatek,mt6315-regulator            ö          regulators     vbuck1          „Vbcpu           “ €        « 7        Ã                              ß      vbuck3          „Vlcpu           “ €        « 7        Ã                              ß            pmic@7            mediatek,mt6315-regulator            ö          regulators     vbuck1          „Vgpu            “ €        « 5         Ã                                         7  '         Ò                  mailbox@10228000              mediatek,mt8192-gce          ö    "€       @         <       Ë               T            £              Ðgce          Ò   ^      clock-controller@10720000             mediatek,mt8192-scp_adsp             ö    r                  –           `fail          serial@11002000       *    mediatek,mt8192-uart mediatek,mt6577-uart            ö                      <       m                £               	  Ðbaud bus            `okay          serial@11003000       *    mediatek,mt8192-uart mediatek,mt6577-uart            ö     0                <       n                £               	  Ðbaud bus          	  `disabled          clock-controller@11007000             mediatek,mt8192-imp_iic_wrap_c           ö     p                 –         spi@1100a000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö                      <       Ÿ                £      M                    Ðparent-clk sel-clk spi-clk        	  `disabled          thermal-sensor@1100b000           mediatek,mt8192-lvts-ap          ö     °                <       ©                £      	        g               n   '        zlvts-calib-data-1           ‹            Ò   |      svs@1100bc00              mediatek,mt8192-svs          ö     ¼                <       §                £      	        Ðmain            n   (   '      (  zsvs-calibration-data t-calibration-data         g              ¡svs_rst       pwm@1100e000              mediatek,mt8183-disp-pwm             ö     à                <       «               ­            £      !      8        Ðmain mm         `okay            ¸default         Æ   )         Ò   }      spi@11010000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö                     <                        £      M            <        Ðparent-clk sel-clk spi-clk          `okay            Ð            ¸default         Æ   *   ec@0              google,cros-ec-spi           ö            #                 ä -ÆÀ        ¸default         Æ   +         ö                     +       pwm           google,cros-ec-pwm          ­           `okay             Ò   ¥      i2c-tunnel            google,cros-ec-i2c-tunnel                                    +       sbs-battery@b             sbs,sbs-battery          ö                      *            regulator@0           google,cros-ec-regulator             ö            “ w@        « 2Z          Ò   \      regulator@1           google,cros-ec-regulator             ö           “ 2Z         « 2Z          Ò   [      typec             google,cros-ec-typec                         +       connector@0           usb-c-connector          ö            ?left            Edual            Phost            Zsource        connector@1           usb-c-connector          ö           ?right           Edual            Phost            Zsource           keyboard-controller           google,cros-ec-keyb         i           y            Œ     D  ¦  ž ­t x c à á	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	 Ž + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      (  ³               	  	                 spi@11012000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö                     <       ¡                £      M            >        Ðparent-clk sel-clk spi-clk        	  `disabled          spi@11013000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö    0                <       ¢                £      M            ?        Ðparent-clk sel-clk spi-clk        	  `disabled          spi@11018000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö    €                <       £                £      M            L        Ðparent-clk sel-clk spi-clk        	  `disabled          spi@11019000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö    �                <       ¤                £      M            M        Ðparent-clk sel-clk spi-clk          `okay            È      %           Ð            ¸default         Æ   ,   tpm@0             google,cr50          ö            #      «           ä B@        ¸default         Æ   -         spi@1101d000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö    Ð                <       ¥                £      M            m        Ðparent-clk sel-clk spi-clk        	  `disabled          spi@1101e000          (    mediatek,mt8192-spi mediatek,mt6765-spi                      +             ö    à                <       ¦                £      M            n        Ðparent-clk sel-clk spi-clk        	  `disabled          scp@10500000              mediatek,mt8192-scp       0   ö    P             r             p        €         ÿsram cfg l1tcm          <      ³                £              Ðmain            `okay            Ñmediatek/mt8192/scp.img         ß   .        ¸default         Æ   /         Ò   r   cros-ec-rpmsg             google,cros-ec-rpmsg            ícros-ec-rpmsg            usb@11200000          '    mediatek,mt8192-xhci mediatek,mtk-xhci            ö                   >              	  ÿmac ippc            #          a               host               0      1           ü      "      #              ]      ]          £      7   2               R      $  Ðsys_ck ref_ck mcu_ck dma_ck xhci_ck          ö           3      f        `okay            -   4        ;   5      syscon@11210000           mediatek,mt8192-audsys syscon            ö    !                   –            Ò   8   mt8192-afe-pcm            mediatek,mt8192-audio           <       Ê               g   6         	  ¡audiosys            G   2        Ü           [           m   7         ¼   £   8       8      8      8      8      8      8      8      8      8      8   	   8   
   8      8      8      8      8      8      8      8         /      :                  H      /      e      0      i      +      g      ,      k      ;      <      =      >      ?      @      A      B      C      D      Ž      �      �      ‘      ’      “      ”      •      –      —      ˜      7        u  Ðaud_afe_clk aud_dac_clk aud_dac_predis_clk aud_adc_clk aud_adda6_adc_clk aud_apll22m_clk aud_apll24m_clk aud_apll1_tuner_clk aud_apll2_tuner_clk aud_tdm_clk aud_tml_clk aud_nle aud_dac_hires_clk aud_adc_hires_clk aud_adc_hires_tml aud_adda6_adc_hires_clk aud_3rd_dac_clk aud_3rd_dac_predis_clk aud_3rd_dac_tml aud_3rd_dac_hires_clk aud_infra_clk aud_infra_26m_clk top_mux_audio top_mux_audio_int top_mainpll_d4_d4 top_mux_aud_1 top_apll1_ck top_mux_aud_2 top_apll2_ck top_mux_aud_eng1 top_apll1_d4 top_mux_aud_eng2 top_apll2_d4 top_i2s0_m_sel top_i2s1_m_sel top_i2s2_m_sel top_i2s3_m_sel top_i2s4_m_sel top_i2s5_m_sel top_i2s6_m_sel top_i2s7_m_sel top_i2s8_m_sel top_i2s9_m_sel top_apll12_div0 top_apll12_div1 top_apll12_div2 top_apll12_div3 top_apll12_div4 top_apll12_divb top_apll12_div5 top_apll12_div6 top_apll12_div7 top_apll12_div8 top_apll12_div9 top_mux_audio_h top_clk26m_clk             Ò   ˆ         pcie@11230000             mediatek,mt8192-pcie             êpci          ö    #                	  ÿpcie-mac                         +         0   £      +      '      *      j      ^      \      /  Ðpl_250m tl_26m tl_96m tl_32k peri_26m top_133m          ü      )              Q        <       û               {       ÿ      8  k‚                      €  �       €      €       €          Œ           …                     `  ˜                  9                      9                     9                     9           ¸default         Æ   :        ß   ;   interrupt-controller             ´                     Œ            Ò   9      pcie@0,0             êpci          ö                            ¦           {                           +            k   wifi@0,0          (   ö                                               spi@11234000              mediatek,mt8192-nor          ö    #@        à        <      ¯                £      :      w      ]        Ðspi sf axi          ü      :              b                     +            `okay            ¸default         Æ   <   flash@0            winbond,w25q64jwm jedec,spi-nor          ö            äu         °           Á            thermal-sensor@11278000           mediatek,mt8192-lvts-mcu             ö    '€                <       ª                £      	        g              n   '        zlvts-calib-data-1           ‹            Ò   s      efuse@11c10000        %    mediatek,mt8192-efuse mediatek,efuse             ö    Á                              +      socinfo-data1@44             ö   D         socinfo-data2@50             ö   P         data1@1c0            ö  À   X         Ò   '      calib@580            ö  €   h         Ò   (         i2c@11cb0000              mediatek,mt8192-i2c           ö    Ë             !s        €        <       s                £   =          x      	  Ðmain dma             ª                        +            `okay             Ú €        ¸default         Æ   >   anx7625@58            analogix,anx7625             ö   X        ¸default         Æ   ?        Ò      )            ß      *            ë   @        ø   A           B   ports                        +       port@0           ö       endpoint               C         Ò   b         port@1           ö      endpoint               D         Ò   F            aux-bus    panel         
    edp-panel           "   B        /   E   port       endpoint               F         Ò   D                     clock-controller@11cb1000             mediatek,mt8192-imp_iic_wrap_e           ö    Ë                 –            Ò   =      i2c@11d00000              mediatek,mt8192-i2c           ö    Ð             !v       €        <       w                £   G          x      	  Ðmain dma             ª                        +            `okay             Ú €        ¸default         Æ   H      i2c@11d01000              mediatek,mt8192-i2c           ö    Ð            !w€      €        <       x                £   G         x      	  Ðmain dma             ª                        +          	  `disabled          i2c@11d02000              mediatek,mt8192-i2c           ö    Ð             !y       €        <       y                £   G         x      	  Ðmain dma             ª                        +          	  `disabled          clock-controller@11d03000             mediatek,mt8192-imp_iic_wrap_s           ö    Ð0                 –            Ò   G      i2c@11d20000              mediatek,mt8192-i2c           ö    Ò             !q        €        <       q                £   I          x      	  Ðmain dma             ª                        +            `okay             Ú €        ¸default         Æ   J   audio-codec@1a           ö           #                 9           H           Y   K        e   K        r   K        �   4          realtek,rt5682i         �           ¤   L         Ò   ¤         i2c@11d21000              mediatek,mt8192-i2c           ö    Ò            !q€      €        <       r                £   I         x      	  Ðmain dma             ª                        +            `okay             Ú €        °  18        ¸default         Æ   M   trackpad@15           elan,ekth3000            ö           #                 ¸default         Æ   N        Á   O         ö         i2c@11d22000              mediatek,mt8192-i2c           ö    Ò             !s€      €        <       t                £   I         x      	  Ðmain dma             ª                        +          	  `disabled          clock-controller@11d23000              mediatek,mt8192-imp_iic_wrap_ws          ö    Ò0                 –            Ò   I      i2c@11e00000              mediatek,mt8192-i2c           ö    à             !u        €        <       u                £   P          x      	  Ðmain dma             ª                        +          	  `disabled          clock-controller@11e01000             mediatek,mt8192-imp_iic_wrap_w           ö    à                 –            Ò   P      t-phy@11e40000        .    mediatek,mt8192-tphy mediatek,generic-tphy-v2                        +           k        ä        usb-phy@0            ö                £           Ðref         Ì            Ò   0      usb-phy@700          ö     	          £           Ðref         Ì            Ò   1         dsi-phy@11e50000              mediatek,mt8183-mipi-tx          ö    å                  £   2   
         –            Ì             ¿mipi_tx0_pll            `okay             Ò   a      i2c@11f00000              mediatek,mt8192-i2c           ö    ð             !p€       €        <       p                £   Q          x      	  Ðmain dma             ª                        +            `okay             Ú €        ¸default         Æ   R   touchscreen@10           ö           #                 ¸default         Æ   S          elan,ekth3500            i2c@11f01000              mediatek,mt8192-i2c           ö    ð            !u€       €        <       v                £   Q         x      	  Ðmain dma             ª                        +          	  `disabled          clock-controller@11f02000             mediatek,mt8192-imp_iic_wrap_n           ö    ð                  –            Ò   Q      clock-controller@11f10000             mediatek,mt8192-msdc_top             ö    ñ                  –            Ò   T      mmc@11f60000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc           ö    ö             õ                 <       c             8   £         T   	   T      T      T      T      T         3  Ðsource hclk source_cg sys_cg pclk_cg axi_cg ahb_cg          `okay            ¸default state_uhs           Æ   U        ×   V        ·           èëÂ         á   W        í   X         ú         	         	         	*         	7         	H        	b (         	q         	y         	      mmc@11f70000          (    mediatek,mt8192-mmc mediatek,mt8183-mmc           ö    ÷             Ç                 <       g             8   £         T   
   T      T      T      T      T         3  Ðsource hclk source_cg sys_cg pclk_cg axi_cg ahb_cg          `okay            ¸default state_uhs           Æ   Y        ×   Z        ·           èëÂ         	�                 á   [        í   \         	–         	§         	´         	q         	Â      gpu@13000000          )    mediatek,mt8192-mali arm,mali-valhall-jm             ö             @       0  <      m             l             k               job mmu gpu          £   2         (  m   7      7      7      7      7           	Écore0 core1 core2 core3 core4           	Ü   ]        `okay            	ð         clock-controller@13fbf000             mediatek,mt8192-mfgcfg           ö    ûð                 –         syscon@14000000           mediatek,mt8192-mmsys syscon             ö                       –           ò           	ü   ^          ^              
   ^                   Ò         mutex@14001000            mediatek,mt8192-disp-mutex           ö                     <       ü                £               
   ^                 
  ²  ³        m   7   	      smi@14002000              mediatek,mt8192-smi-common           ö                        £                                Ðapb smi gals0 gals1         m   7   	         Ò   _      larb@14003000             mediatek,mt8192-smi-larb             ö     0                
/            
@   _         £              Ðapb smi         m   7   	         Ò   c      larb@14004000             mediatek,mt8192-smi-larb             ö     @                
/           
@   _         £              Ðapb smi         m   7   	         Ò   d      ovl@14005000              mediatek,mt8192-disp-ovl             ö     P                <       þ                £              
M   `      `           m   7   	        
   ^     P          ovl@14006000              mediatek,mt8192-disp-ovl-2l          ö     `                <       ÿ               m   7   	         £              
M   `   "   `            
   ^     `          rdma@14007000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma          ö     p                <                       £              
M   `           
T           m   7   	        
   ^     p          color@14009000        6    mediatek,mt8192-disp-color mediatek,mt8173-disp-color            ö     �                <                     m   7   	         £              
   ^     �          ccorr@1400a000            mediatek,mt8192-disp-ccorr           ö                      <                     m   7   	         £      	        
   ^                aal@1400b000          2    mediatek,mt8192-disp-aal mediatek,mt8183-disp-aal            ö     °                <                     m   7   	         £              
   ^     °          gamma@1400c000        6    mediatek,mt8192-disp-gamma mediatek,mt8183-disp-gamma            ö     À                <                     m   7   	         £              
   ^     À          postmask@1400d000             mediatek,mt8192-disp-postmask            ö     Ð                <                     m   7   	         £              
   ^     Ð          dither@1400e000       8    mediatek,mt8192-disp-dither mediatek,mt8183-disp-dither          ö     à                <                     m   7   	         £      
        
   ^     à          dsi@14010000              mediatek,mt8183-dsi          ö                     <      	                £                a        Ðengine digital hs              a        
ldphy            m   7   	        g              `okay       port       endpoint               b         Ò   C            ovl@14014000              mediatek,mt8192-disp-ovl-2l          ö    @                <                     m   7   	         £              
M   `   #   `   !        
   ^     @          rdma@14015000         4    mediatek,mt8192-disp-rdma mediatek,mt8183-disp-rdma          ö    P                <                     m   7   	         £              
M   `   %        
T           
   ^     P          dpi@14016000              mediatek,mt8192-dpi          ö    `                <                      £      !         2           Ðpixel engine pll          	  `disabled          m4u@1401d000              mediatek,mt8192-m4u          ö    Ð              <  
v   c   d   e   f   g   h   i   j   k   l   m   n   o   p   q        <                      £              Ðbclk            m   7   	        
…            Ò   `      clock-controller@15020000             mediatek,mt8192-imgsys           ö                      –            Ò         larb@1502e000             mediatek,mt8192-smi-larb             ö    à                
/   	        
@   _         £                      Ðapb smi         m   7            Ò   i      clock-controller@15820000             mediatek,mt8192-imgsys2          ö    ‚                  –            Ò         larb@1582e000             mediatek,mt8192-smi-larb             ö    ‚à                
/           
@   _         £                      Ðapb smi         m   7            Ò   j      video-codec@16000000              mediatek,mt8192-vcodec-dec           ö                      
’   r        
M   `   €                     +           k                    `    video-codec@10000             mediatek,mtk-vcodec-lat          ö                      <      ª             @  
M   `       `   ¡   `   ¢   `   £   `   ¤   `   ¥   `   ¦   `   §      (   £      4                            F        Ðsel soc-vdec soc-lat vdec top           ü      4              F        m   7         video-codec@25000             mediatek,mtk-vcodec-core             ö     P                <      ©             X  
M   `   €   `   �   `   ‚   `   ƒ   `   „   `   …   `   †   `   ‡   `   ˆ   `   ‰   `   Š      (   £      4   !      !      !          F        Ðsel soc-vdec soc-lat vdec top           ü      4              F        m   7            larb@1600d000             mediatek,mt8192-smi-larb             ö     Ð                
/           
@   _         £                        Ðapb smi         m   7            Ò   g      clock-controller@1600f000             mediatek,mt8192-vdecsys_soc          ö     ð                 –            Ò          larb@1602e000             mediatek,mt8192-smi-larb             ö    à                
/           
@   _         £   !       !            Ðapb smi         m   7            Ò   f      clock-controller@1602f000             mediatek,mt8192-vdecsys          ö    ð                 –            Ò   !      clock-controller@17000000             mediatek,mt8192-vencsys          ö                       –            Ò         larb@17010000             mediatek,mt8192-smi-larb             ö                     
/           
@   _         £                     Ðapb smi         m   7            Ò   h      vcodec@17020000           mediatek,mt8192-vcodec-enc           ö                    X  
M   `   à   `   á   `   â   `   ã   `   ä   `   å   `   æ   `   ç   `   è   `   í   `   î        <      5               
’   r        m   7            £            	  Ðvenc_sel            ü      3              W      clock-controller@1a000000             mediatek,mt8192-camsys           ö                       –            Ò   "      larb@1a001000             mediatek,mt8192-smi-larb             ö                     
/           
@   _         £   "      "            Ðapb smi         m   7            Ò   k      larb@1a002000             mediatek,mt8192-smi-larb             ö                      
/           
@   _         £   "      "           Ðapb smi         m   7            Ò   l      larb@1a00f000             mediatek,mt8192-smi-larb             ö     ð                
/           
@   _         £   #      #            Ðapb smi         m   7            Ò   m      larb@1a010000             mediatek,mt8192-smi-larb             ö                     
/           
@   _         £   $      $            Ðapb smi         m   7            Ò   n      larb@1a011000             mediatek,mt8192-smi-larb             ö                    
/           
@   _         £   %       %           Ðapb smi         m   7            Ò   o      clock-controller@1a04f000             mediatek,mt8192-camsys_rawa          ö    ð                 –            Ò   #      clock-controller@1a06f000             mediatek,mt8192-camsys_rawb          ö    ð                 –            Ò   $      clock-controller@1a08f000             mediatek,mt8192-camsys_rawc          ö    ð                 –            Ò   %      clock-controller@1b000000             mediatek,mt8192-ipesys           ö                       –            Ò         larb@1b00f000             mediatek,mt8192-smi-larb             ö     ð                
/           
@   _         £                    Ðapb smi         m   7   
         Ò   q      larb@1b10f000             mediatek,mt8192-smi-larb             ö    ð                
/           
@   _         £                     Ðapb smi         m   7   
         Ò   p      clock-controller@1f000000             mediatek,mt8192-mdpsys           ö                       –            Ò         larb@1f002000             mediatek,mt8192-smi-larb             ö                      
/           
@   _         £                    Ðapb smi         m   7            Ò   e         thermal-zones      cpu0-thermal            
Ÿ  è        
­   ú        
Ã   s      trips      trip-alert          
Ó L        
ß  Ð         Epassive          Ò   t      trip-crit           
Ó †         
ß  Ð      	   Ecritical             cooling-maps       map0            
ê   t      0  
ï   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            
Ÿ  è        
­   ú        
Ã   s      trips      trip-alert          
Ó L        
ß  Ð         Epassive          Ò   u      trip-crit           
Ó †         
ß  Ð      	   Ecritical             cooling-maps       map0            
ê   u      0  
ï   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            
Ÿ  è        
­   ú        
Ã   s      trips      trip-alert          
Ó L        
ß  Ð         Epassive          Ò   v      trip-crit           
Ó †         
ß  Ð      	   Ecritical             cooling-maps       map0            
ê   v      0  
ï   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            
Ÿ  è        
­   ú        
Ã   s      trips      trip-alert          
Ó L        
ß  Ð         Epassive          Ò   w      trip-crit           
Ó †         
ß  Ð      	   Ecritical             cooling-maps       map0            
ê   w      0  
ï   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            
Ÿ  è        
­   ú        
Ã   s       trips      trip-alert          
Ó L        
ß  Ð         Epassive          Ò   x      trip-crit           
Ó †         
ß  Ð      	   Ecritical             cooling-maps       map0            
ê   x      0  
ï   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            
Ÿ  è        
­   ú        
Ã   s      trips      trip-alert          
Ó L        
ß  Ð         Epassive          Ò   y      trip-crit           
Ó †         
ß  Ð      	   Ecritical             cooling-maps       map0            
ê   y      0  
ï   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            
Ÿ  è        
­   ú        
Ã   s      trips      trip-alert          
Ó L        
ß  Ð         Epassive          Ò   z      trip-crit           
Ó †         
ß  Ð      	   Ecritical             cooling-maps       map0            
ê   z      0  
ï   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            
Ÿ  è        
­   ú        
Ã   s      trips      trip-alert          
Ó L        
ß  Ð         Epassive          Ò   {      trip-crit           
Ó †         
ß  Ð      	   Ecritical             cooling-maps       map0            
ê   {      0  
ï   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            
Ÿ  è        
­   ú        
Ã   |      trips      trip-alert          
Ó L        
ß  Ð         Epassive       trip-crit           
Ó †         
ß  Ð      	   Ecritical                vpu1-thermal            
Ÿ  è        
­   ú        
Ã   |   	   trips      trip-alert          
Ó L        
ß  Ð         Epassive       trip-crit           
Ó †         
ß  Ð      	   Ecritical                gpu-thermal         
Ÿ  è        
­   ú        
Ã   |   
   trips      trip-alert          
Ó L        
ß  Ð         Epassive       trip-crit           
Ó †         
ß  Ð      	   Ecritical                gpu1-thermal            
Ÿ  è        
­   ú        
Ã   |      trips      trip-alert          
Ó L        
ß  Ð         Epassive       trip-crit           
Ó †         
ß  Ð      	   Ecritical                infra-thermal           
Ÿ  è        
­   ú        
Ã   |      trips      trip-alert          
Ó L        
ß  Ð         Epassive       trip-crit           
Ó †         
ß  Ð      	   Ecritical                cam-thermal         
Ÿ  è        
­   ú        
Ã   |      trips      trip-alert          
Ó L        
ß  Ð         Epassive       trip-crit           
Ó †         
ß  Ð      	   Ecritical                md0-thermal         
Ÿ  è        
­   ú        
Ã   |      trips      trip-alert          
Ó L        
ß  Ð         Epassive       trip-crit           
Ó †         
ß  Ð      	   Ecritical                md1-thermal         
Ÿ  è        
­   ú        
Ã   |      trips      trip-alert          
Ó L        
ß  Ð         Epassive       trip-crit           
Ó †         
ß  Ð      	   Ecritical                md2-thermal         
Ÿ  è        
­   ú        
Ã   |      trips      trip-alert          
Ó L        
ß  Ð         Epassive       trip-crit           
Ó †         
ß  Ð      	   Ecritical                   chosen          
þserial0:115200n8          memory@40000000          êmemory           ö    @       €         backlight-lcd0            pwm-backlight           
   }     ¡         "   ~        Ò      ˜                  ÿ        !  ÿ        8  @         Ò   E      dmic-codec            dmic-codec          Q           ^   2      regulator-1v0-dpbrdg              regulator-fixed         „pp1000_dpbrdg           ¸default         Æ           “ B@        « B@         n         �        “                  ˜   €      regulator-1v0-mipibrdg            regulator-fixed         „pp1000_mipibrdg         ¸default         Æ   �        “ B@        « B@         n         �        “      �            ˜   €         Ò   @      regulator-1v8-dpbrdg              regulator-fixed         „pp1800_dpbrdg           ¸default         Æ   ‚         n         �        “      ~            ˜   K      regulator-1v8-g           regulator-fixed         „pp1800_ldo_g             ß         �        “ w@        « w@        ˜   4      regulator-1v8-mipibrdg            regulator-fixed         „pp1800_mipibrdg         ¸default         Æ   ƒ         n         �        “      €            ˜   K         Ò   A      regulator-3v3-dpbrdg              regulator-fixed         „pp3300_dpbrdg           ¸default         Æ   „         n         �        “                  ˜   4      regulator-3v3-g           regulator-fixed       	  „pp3300_g             ß         �        “ 2Z         « 2Z         ˜   ~         Ò   4      regulator-3v3-z           regulator-fixed         „pp3300_ldo_z             ß         �        “ 2Z         « 2Z         ˜   ~         Ò   L      regulator-3v3-mipibrdg            regulator-fixed         „pp3300_mipibrdg         ¸default         Æ   …         n         �        “                  ˜   4        £ ¡          Ò   B      regulator-3v3-u           regulator-fixed       	  „pp3300_u             ß         �        “ 2Z         « 2Z         ˜   4         Ò   O      regulator-3v3-wlan            regulator-fixed         „pp3300_wlan          ß         �        “ 2Z         « 2Z         ¸default         Æ   †         n        “      �          regulator-5v0-a           regulator-fixed       	  „pp5000_a             ß         �        “ LK@        « LK@        ˜   ~         Ò   5      regulator-var-sys             regulator-fixed       
  „ppvar_sys            ß         �         Ò   ~      reserved-memory                      +            k   scp@50000000              shared-dma-pool          ö    P       �           ³         Ò   .      wifi@c0000000             restricted-dma-pool          ö    À                   Ò   ;         audio-codec           realtek,rt1015p         ¸default         Æ   ‡        º      “            H             Ò   £      sound           Ä   ˆ     É  ¸aud_clk_mosi_off aud_clk_mosi_on aud_dat_mosi_off aud_dat_mosi_on aud_dat_miso_off aud_dat_miso_on vow_dat_miso_off vow_dat_miso_on vow_clk_miso_off vow_clk_miso_on aud_nle_mosi_off aud_nle_mosi_on aud_dat_miso2_off aud_dat_miso2_on aud_gpio_i2s3_off aud_gpio_i2s3_on aud_gpio_i2s8_off aud_gpio_i2s8_on aud_gpio_i2s9_off aud_gpio_i2s9_on aud_dat_mosi_ch34_off aud_dat_mosi_ch34_on aud_dat_miso_ch34_off aud_dat_miso_ch34_on aud_gpio_tdm_off aud_gpio_tdm_on            Æ   ‰        ×   Š        Ö   ‹        à   Œ        ê   �        ô   Ž        þ   �           �           ‘           ’        &   “        1   ”        <   •        G   –        R   —        ]   ˜        h   ™        s   š        ~   ›        ‰   œ        ”   �        Ÿ   ž        ª   Ÿ        µ            À   ¡        Ë   ¢      &    mediatek,mt8192_mt6359_rt1015p_rt5682      speaker-codecs          Ö   £      headset-codec           Ö   ¤             pwmleds       	    pwm-leds       led         àkbd_backlight           é            
   ¥            ï  ÿ            	compatible interrupt-parent #address-cells #size-cells model chassis-type ovl0 ovl-2l0 ovl-2l2 rdma0 rdma4 i2c0 i2c1 i2c2 i2c3 i2c7 mmc0 mmc1 serial0 #clock-cells clocks clock-div clock-mult clock-output-names phandle clock-frequency device_type reg enable-method cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache performance-domains capacity-dmips-mhz #cooling-cells cpu cache-level cache-unified entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us interrupts opp-shared opp-hz opp-microvolt dma-ranges #performance-domain-cells #interrupt-cells #redistributor-regions interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges gpio-line-names pinmux output-low input-enable bias-pull-up drive-strength drive-strength-microamp bias-disable bias-pull-down output-high #power-domain-cells clock-names mediatek,infracfg domain-supply assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 mediatek,mic-type-2 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes regulator-coupled-with regulator-coupled-max-spread #mbox-cells status resets nvmem-cells nvmem-cell-names #thermal-sensor-cells reset-names #pwm-cells pinctrl-names pinctrl-0 mediatek,pad-select spi-max-frequency wakeup-source google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count label power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap cs-gpios firmware-name memory-region mediatek,rpmsg-name interrupt-names phys mediatek,syscon-wakeup vusb33-supply vbus-supply mediatek,apmixedsys mediatek,topckgen power-domains bus-range interrupt-map-mask interrupt-map num-lanes spi-rx-bus-width spi-tx-bus-width enable-gpios reset-gpios vdd10-supply vdd18-supply vdd33-supply remote-endpoint power-supply backlight realtek,jd-src #sound-dai-cells AVDD-supply DBVDD-supply LDO1-IN-supply MICVDD-supply realtek,btndet-delay VBAT-supply clock-stretch-ns vcc-supply #phy-cells pinctrl-1 vmmc-supply vqmmc-supply cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v supports-cqe cap-mmc-hw-reset mmc-hs400-enhanced-strobe hs400-ds-delay no-sdio no-sd non-removable cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc power-domain-names operating-points-v2 mali-supply mboxes mediatek,gce-client-reg mediatek,gce-events mediatek,larb-id mediatek,smi iommus mediatek,rdma-fifo-size phy-names mediatek,larbs #iommu-cells mediatek,scp polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path pwms brightness-levels num-interpolated-steps default-brightness-level num-channels wakeup-delay-ms enable-active-high regulator-boot-on gpio vin-supply off-on-delay-us no-map sdb-gpios mediatek,platform pinctrl-2 pinctrl-3 pinctrl-4 pinctrl-5 pinctrl-6 pinctrl-7 pinctrl-8 pinctrl-9 pinctrl-10 pinctrl-11 pinctrl-12 pinctrl-13 pinctrl-14 pinctrl-15 pinctrl-16 pinctrl-17 pinctrl-18 pinctrl-19 pinctrl-20 pinctrl-21 pinctrl-22 pinctrl-23 pinctrl-24 pinctrl-25 sound-dai function color max-brightness 