Ðþí v†   8 gÄ   (            Â gŒ                             `    google,dojo-sku7 google,dojo-sku5 google,dojo-sku3 google,dojo-sku1 google,dojo mediatek,mt8195                                  +            7HP Dojo (sku 1, 3, 5, 7) board           =convertible    aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/mailbox@10320000            a/soc/mailbox@10330000            f/soc/hdr-engine@1c114000             m/soc/mutex@1c016000          t/soc/mutex@1c101000          {/soc/vpp-merge@1c10c000          ‚/soc/vpp-merge@1c10d000          ‰/soc/vpp-merge@1c10e000          �/soc/vpp-merge@1c10f000          —/soc/vpp-merge@1c110000          ž/soc/dma-controller@1c104000             ©/soc/dma-controller@1c105000             ´/soc/dma-controller@1c106000             ¿/soc/dma-controller@1c107000             Ê/soc/dma-controller@1c108000             Õ/soc/dma-controller@1c109000             à/soc/dma-controller@1c10a000             ë/soc/dma-controller@1c10b000             ö/soc/i2c@11e00000            û/soc/i2c@11e01000            /soc/i2c@11e02000           /soc/i2c@11e03000           
/soc/i2c@11e04000           /soc/i2c@11d00000           /soc/i2c@11d02000           /soc/mmc@11230000           /soc/mmc@11240000           #/soc/serial@11001100          cpus                         +       cpu@0           +cpu           arm,cortex-a55          7            ;psci            I               ]ec3@        m  4        €              �  €         �   @        ¯   €        ¼  €         É   @        Û   €        è           ù                               cpu@100         +cpu           arm,cortex-a55          7           ;psci            I               ]ec3@        m  4        €              �  €         �   @        ¯   €        ¼  €         É   @        Û   €        è           ù                               cpu@200         +cpu           arm,cortex-a55          7           ;psci            I               ]ec3@        m  4        €              �  €         �   @        ¯   €        ¼  €         É   @        Û   €        è           ù                               cpu@300         +cpu           arm,cortex-a55          7           ;psci            I               ]ec3@        m  4        €              �  €         �   @        ¯   €        ¼  €         É   @        Û   €        è           ù                               cpu@400         +cpu           arm,cortex-a78          7           ;psci            I              ]�fÔÀ        m           €              �           �   @        ¯           ¼           É   @        Û           è   	        ù              
                 cpu@500         +cpu           arm,cortex-a78          7           ;psci            I              ]�fÔÀ        m           €              �           �   @        ¯           ¼           É   @        Û           è   	        ù              
                 cpu@600         +cpu           arm,cortex-a78          7           ;psci            I              ]�fÔÀ        m           €              �           �   @        ¯           ¼           É   @        Û           è   	        ù              
                 cpu@700         +cpu           arm,cortex-a78          7           ;psci            I              ]�fÔÀ        m           €              �           �   @        ¯           ¼           É   @        Û           è   	        ù              
                 cpu-map    cluster0       core0                    core1                    core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state          ,           C        T   2        e   _        u  D                 cpu-retention-b           arm,idle-state          ,           C        T   -        e   Œ        u  ä                 cpu-off-l             arm,idle-state          ,          C        T   7        e   ›        u  H                 cpu-off-b             arm,idle-state          ,          C        T   2        e   È        u  è                    l2-cache0             cache           †           ’           Ÿ   @        ±           è            ’                 l2-cache1             cache           †           ’           Ÿ   @        ±           è            ’           	      l3-cache              cache           †           ’            Ÿ   @        ±            ’                    dsu-pmu           arm,dsu-pmu                                 «                                °fail          dmic-codec            dmic-codec          ·           Ä   2      mt8195-sound            Ô           °okay            æ         }  ôDL10_FE DPTX_BE ETDM1_IN_BE ETDM2_IN_BE ETDM1_OUT_BE ETDM2_OUT_BE UL_SRC1_BE AFE_SOF_DL2 AFE_SOF_DL3 AFE_SOF_UL4 AFE_SOF_UL5            default                  [  Headphone HPOL Headphone HPOR IN1P Headset Mic Right Spk Right BE_OUT Left Spk Left BE_OUT        '    mediatek,mt8195_mt6359_max98390_rt5682           7m8195_m98390_5682s     mm-dai-link         ,ETDM1_IN_BE         6cpu       hs-playback-dai-link            ,ETDM1_OUT_BE            6cpu    codec           L                hs-capture-dai-link         ,ETDM2_IN_BE         6cpu    codec           L                spk-playback-dai-link           ,ETDM2_OUT_BE            6cpu    codec           L               displayport-dai-link            ,DPTX_BE    codec           L               fixed-factor-clock-13m            fixed-factor-clock          V            c           j           t           clk13m             3      oscillator-26m            fixed-clock         V            ]Œº€        clk26m                   oscillator-32k            fixed-clock         V            ]  €         clk32k        performance-controller@11bc10             mediatek,cpufreq-hw          7     ¼            ½0               ’                    opp-table-gpu             operating-points-v2          ¬           ~   opp-390000000           ·    >í€        ¾ 	‰h      opp-410000000           ·    p€        ¾ 	¡Ò      opp-431000000           ·    °‰À        ¾ 	¡Ò      opp-473000000           ·    1h@        ¾ 	º<      opp-515000000           ·    ²FÀ        ¾ 	º<      opp-556000000           ·    !#ã         ¾ 	Ò¦      opp-598000000           ·    #¤Á€        ¾ 	ë      opp-640000000           ·    &%          ¾ 	ë      opp-670000000           ·    'ïc€        ¾ 
ä      opp-700000000           ·    )¹'         ¾ 
L¸      opp-730000000           ·    +‚ê€        ¾ 
}Œ      opp-760000000           ·    -L®         ¾ 
®`      opp-790000000           ·    /q€        ¾ 
ß4      opp-820000000           ·    0à5         ¾       opp-850000000           ·    2©ø€        ¾ @Ü      opp-880000000           ·    4s¼         ¾ q°         pmu-a55           arm,cortex-a55-pmu                                         pmu-a78           arm,cortex-a78-pmu                                         psci              arm,psci-1.0            Bsmc       timer             arm,armv8-timer                   @                                                
             soc                      +             simple-bus           Ì        Ó                          interrupt-controller@c000000              arm,gic-v3          Þ           ï                                 7                                           	                              ppi-partitions     interrupt-partition-0           ;                             interrupt-partition-1           ;                                   syscon@10000000            mediatek,mt8195-topckgen syscon         7                      V              "      syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          7                     V           D              #      syscon@10003000           mediatek,mt8195-pericfg syscon          7     0                V              I      pinctrl@10005000              mediatek,mt8195-pinctrl       €  7     P            Ñ             Ó             Ô             â             ë             ô              °              B  Qiocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            [        k           w              �                         ë               Þ            ƒ        default                 >  §I2S_SPKR_MCLK I2S_SPKR_DATAIN I2S_SPKR_LRCK I2S_SPKR_BCLK EC_AP_INT_ODL AP_FLASH_WP_L TCHPAD_INT_ODL EDP_HPD_1V8 AP_I2C_CAM_SDA AP_I2C_CAM_SCL AP_I2C_TCHPAD_SDA_1V8 AP_I2C_TCHPAD_SCL_1V8 AP_I2C_AUD_SDA AP_I2C_AUD_SCL AP_I2C_TPM_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 EC_AP_HPD_OD  PCIE_NVME_RST_L PCIE_NVME_CLKREQ_ODL PCIE_RST_1V8_L PCIE_CLKREQ_1V8_ODL PCIE_WAKE_1V8_ODL CLK_24M_CAM0 CAM1_SEN_EN AP_I2C_PWR_SCL_1V8 AP_I2C_PWR_SDA_1V8 AP_I2C_MISC_SCL AP_I2C_MISC_SDA EN_PP5000_HDMI_X AP_HDMITX_HTPLG  AP_HDMITX_SCL_1V8 AP_HDMITX_SDA_1V8 AP_RTC_CLK32K AP_EC_WATCHDOG_L SRCLKENA0 SRCLKENA1 PWRAP_SPI0_CS_L PWRAP_SPI0_CK PWRAP_SPI0_MOSI PWRAP_SPI0_MISO SPMI_SCL SPMI_SDA    I2S_HP_DATAIN I2S_HP_MCLK I2S_HP_BCK I2S_HP_LRCK I2S_HP_DATAOUT SD_CD_ODL EN_PP3300_DISP_X TCHSCR_RST_1V8_L TCHSCR_REPORT_DISABLE EN_PP3300_WLAN_X BT_KILL_1V8_L I2S_SPKR_DATAOUT WIFI_KILL_1V8_L BEEP_ON SCP_I2C_SENSOR_SCL_1V8 SCP_I2C_SENSOR_SDA_1V8     AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_DAT_MISO2 SCP_VREQ_VAO AP_SPI_GSC_TPM_CLK AP_SPI_GSC_TPM_MOSI AP_SPI_GSC_TPM_CS_L AP_SPI_GSC_TPM_MISO EN_PP1000_CAM_X AP_EDP_BKLTEN  USB3_HUB_RST_L  WLAN_ALERT_ODL EC_IN_RW_ODL GSC_AP_INT_ODL HP_INT_ODL CAM0_RST_L CAM1_RST_L TCHSCR_INT_1V8_L CAM1_DET_L RST_ALC1011_L   BL_PWM_1V8 UART_AP_TX_DBG_RX UART_DBG_TX_AP_RX EN_SPKR AP_EC_WARM_RST_REQ UART_SCP_TX_DBGCON_RX UART_DBGCON_TX_SCP_RX   KPCOL0  MT6315_GPU_INT MT6315_PROC_BC_INT SD_CMD SD_CLK SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_RSTB EMMC_CMD EMMC_CLK EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 EMMC_DSL   MT6360_INT_ODL SCP_JTAG0_TRSTN AP_SPI_EC_CS_L AP_SPI_EC_CLK AP_SPI_EC_MOSI AP_SPI_EC_MISO SCP_JTAG0_TMS SCP_JTAG0_TCK SCP_JTAG0_TDO SCP_JTAG0_TDI AP_SPI_FLASH_CS_L AP_SPI_FLASH_CLK AP_SPI_FLASH_MOSI AP_SPI_FLASH_MISO                 audio-default-pins                pins-cmd-dat          D  ·  E  F  G  H  I  J  K           <  1  2  3  4  5      pins-hp-jack-int-odl            ·  Y          ¾        Ë   e         cr50-irq-default-pins              m   pins-gsc-ap-int-odl         ·  X          ¾         cros-ec-irq-default-pins               ?   pins-ec-ap-int-odl          ·           Ë   e         ¾         edptx-default-pins             µ   pins-cmd-dat            ·           Ë         disp-pwm0-default-pins             C   pins-disp-pwm           ·  R   a         dptx-default-pins              »   pins-cmd-dat            ·           Ë         i2c0-default-pins              d   pins-bus            ·    	         Ø        å  è         i2c1-default-pins              e   pins-bus            ·  
          Ë  è        å  è         i2c2-default-pins              h   pins-bus            ·             Ø        å  è         i2c3-default-pins              l   pins-bus            ·            Ë  è        å  è         i2c4-default-pins              n   pins-bus            ·            Ë  è        ý            i2c5-default-pins              `   pins-bus            ·             Ø        å  è         i2c7-default-pins              a   pins-bus            ·             Ø         mmc0-default-pins              L   pins-cmd-dat          $  ·  ~  }  |  {  w  v  u  t  y         ¾        ý           Ë   e      pins-clk            ·  z        ý              f      pins-rst            ·  x        ý           Ë   e         mmc0-uhs-pins              M   pins-cmd-dat          $  ·  ~  }  |  {  w  v  u  t  y         ¾        ý           Ë   e      pins-clk            ·  z        ý              f      pins-ds         ·          ý              f      pins-rst            ·  x        ý           Ë   e         mmc1-detect-pins               Q   pins-insert         ·  6          Ë         mmc1-default-pins              P   pins-cmd-dat            ·  n  p  q  r  s         ¾        ý           Ë   e      pins-clk            ·  o        ý              f         nor-default-pins               ^   pins-ck-io          ·  Ž  �  �        ý                  pins-cs         ·  Œ        ý            Ë         pcie0-default-pins             Z   pins-bus            ·               Ë         pcie1-default-pins             ]   pins-bus            ·               Ë         panel-pwr-default-pins             Ë   pins-vreg-en            ·  7          pio-default-pins                  pins-wifi-enable            ·  :                  ý         pins-low-power-pd         ,  ·        .   /   0   A   B   C   D   €   �          ¾               pins-low-power-pupd       <  ·  M   N   O   P   S   U   Z   [   ]   ^   _   `   h   i   k          ¾           e      pins-low-power-hdmi-disable         ·         !          ¾               pins-low-power-hdmi-rsel-disable            ·  "   #          ¾         $ø         rt1019p-default-pins               Í   pins-amp-sdb            ·  d          '         scp-default-pins               5   pins-vreq           ·  L         Ø         ¾         spi0-default-pins              >   pins-cs-mosi-clk            ·  „  †  …         Ø      pins-miso           ·  ‡                  subpmic-default-pins               b   pins-subpmic-int-n          ·  ‚          ¾         Ë         trackpad-default-pins              f   pins-int-n          ·            ¾         Ë         touchscreen-default-pins               o   pins-int-n          ·  \          ¾        Ë   e      pins-rst            ·  8                pins-report-sw          ·  9          '            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            7     `           power-controller          !    mediatek,mt8195-power-controller                         +            2              7   power-domain@8          7                        +            2           F       power-domain@9          7   	        c   !      "           Tmfg alt         `   #                     +            2           F   $   power-domain@10         7   
        2          power-domain@11         7           2          power-domain@12         7           2          power-domain@13         7           2          power-domain@14         7           2                power-domain@15         7         Ø  c   "      "      "      "   	   "   @   "   A   "   K   "   à   %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %      %           Tvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           `   #                     +            2      power-domain@16         7         8  c   "   â   &   $   &   %   &   &   &   '   &   (   &   )      D  Tvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         `   #                     +            2      power-domain@17         7           c   "   á   '      '           Tvppsys1 vppsys1-0 vppsys1-1         `   #        2          power-domain@22         7            c   (      (      (      (         $  Twepsys-0 wepsys-1 wepsys-2 wepsys-3         `   #        2          power-domain@23         7           c   )            Tvdec0-0         `   #                     +            2       power-domain@24         7           c   *            Tvdec1-0         `   #        2          power-domain@25         7           c   +            Tvdec2-0         `   #        2             power-domain@26         7           c   ,            Tvenc0-larb          `   #                     +            2       power-domain@27         7           c   -            Tvenc1-larb          `   #        2             power-domain@18         7            c   "   ã   .       .      .         &  Tvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           `   #                     +            2      power-domain@19         7           `   #        2          power-domain@20         7           `   #        2          power-domain@21         7           c   "   Q        Thdmi_tx         2             power-domain@28         7           c   /       /   
        Timg-0 img-1         `   #                     +            2      power-domain@29         7           2          power-domain@30         7           c   "      /      0           Tipe ipe-0 ipe-1         `   #        2             power-domain@31         7         (  c   1       1      1      1      1           Tcam-0 cam-1 cam-2 cam-3 cam-4           `   #                     +            2      power-domain@32         7            2          power-domain@33         7   !        2          power-domain@34         7   "        2                   power-domain@0          7            `   #        2          power-domain@1          7           `   #        2          power-domain@2          7           2          power-domain@3          7           2          power-domain@4          7           c   "   5   "   7        Tcsi_rx_top csi_rx_top1          2          power-domain@5          7           c   2           Tether           2          power-domain@6          7           c   "   X   "   n        Tadsp adsp1                       +            `   #        2      power-domain@7          7            c   "   g   "   "   "   n   #   2        Taudio audio1 audio2 audio3          `   #        2                   watchdog@10007000             mediatek,mt8195-wdt          r        7     p                D              <      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           7     À                V              !      timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         7    p                       	               c   3      pwrap@10024000            mediatek,mt8195-pwrap syscon            7    @                Qpwrap                   ó               c   #      #          	  Tspi wrap            Š   "   $        š   "   Ë   pmic              mediatek,mt6359                  Þ           ±      Þ      adc           mediatek,mt6359-auxadc          Å         mt6359codec         ×           ê         regulators            mediatek,mt6359-regulator      buck_vs1            þvs1          5         % !‘À        =             Y      buck_vgpu11         þvgpu11           €        % 7        m  ˆ        =   È        ‚                   Y      buck_vmodem         þvmodem           €        % Èà        m  *        =   È      buck_vpu            þvpu          €        % 7        m  ˆ        =   È        ‚                   Y      buck_vcore          þvcore            €        % Ö         m  ˆ        =   È        ‚                   Y                 buck_vs2            þvs2          5         % j         =             Y      buck_vpa            þvpa          ¡         % 7±Ð        =  ,      buck_vproc2         þvproc2           €        % 7        m  L        =   È        ‚                buck_vproc1         þvproc1           €        % 7        m  L        =   È        ‚                buck_vcore_sshub            þvcore_sshub          €        % 7      buck_vgpu11_sshub           þvgpu11_sshub             dp        % dp         Y      ldo_vaud18          þvaud18           w@        % w@        =   ð      ldo_vsim1           þvsim1            ð         % /M`      ldo_vibr            þvibr             O€        % 2Z       ldo_vrf12           þvrf12            Èà        % Ö          Y      ldo_vusb            þvusb             -ÆÀ        % -ÆÀ        =  À         Y           J      ldo_vsram_proc2         þvsram_proc2          ¡         % ½¶        m  L        =   ð         Y      ldo_vio18           þvio18            ð         % ýà        =  À         Y           i      ldo_vcamio          þvcamio           ð         % ýà      ldo_vcn18           þvcn18            w@        % w@        =   ð      ldo_vfe28           þvfe28            *¹€        % *¹€        =   x      ldo_vcn13           þvcn13            »         % Ö       ldo_vcn33_1_bt          þvcn33_1_bt           *¹€        % 5gà      ldo_vcn33_1_wifi            þvcn33_1_wifi             *¹€        % 5gà      ldo_vaux18          þvaux18           w@        % w@        =   ð         Y      ldo_vsram_others            þvsram_others             q°        % q°        m  ˆ        =   ð           $      ldo_vefuse          þvefuse           ð         % „€      ldo_vxo22           þvxo22            w@        % !‘À         Y      ldo_vrfck           þvrfck            ã`        % ð       ldo_vrfck_1         þvrfck            ëÀ        % j       ldo_vbif28          þvbif28           *¹€        % *¹€        =   ð      ldo_vio28           þvio28            *¹€        % 2Z          Y      ldo_vemc            þvemc             ,@         % 2Z       ldo_vemc_1          þvemc             &%         % 2Z            N      ldo_vcn33_2_bt          þvcn33_2_bt           *¹€        % 5gà      ldo_vcn33_2_wifi            þvcn33_2_wifi             *¹€        % 5gà      ldo_va12            þva12             O€        % Ö          Y      ldo_va09            þva09             5         % O€      ldo_vrf18           þvrf18            ð         % žP      ldo_vsram_md          	  þvsram_md             ¡         % ½¶        m  *        =   ð      ldo_vufs            þvufs             ð         % ýà         Y           O      ldo_vm18            þvm18             ð         % ýà         Y      ldo_vbbck           þvbbck            Èà        % O€      ldo_vsram_proc1         þvsram_proc1          ¡         % ½¶        m  L        =   ð         Y      ldo_vsim2           þvsim2            ð         % /M`      ldo_vsram_others_sshub          þvsram_others_sshub           ¡         % ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             7    p            �                Qpmif spmimst            c   #      #       "   E      (  Tpmif_sys_ck pmif_tmr_ck spmimst_clk_mux         Š   "   $        š   "   Ë                     +       mt6315@6              mediatek,mt6315-regulator           7          regulators     vbuck1          þVbcpu            €        % 7        =           m  j        ‚                   Y           
            mt6315@7              mediatek,mt6315-regulator           7          regulators     vbuck1          þVgpu             €        % 7        =           m  j        ‚                                     infra-iommu@10315000              mediatek,mt8195-iommu-infra         7    1P       P       P                                                                            š              W      mailbox@10320000              mediatek,mt8195-gce         7    2        @                 â               §           c   #              ¡      mailbox@10330000              mediatek,mt8195-gce         7    3        @                 ä               §           c   #                    scp@10500000              mediatek,mt8195-scp       0  7    P             r             p        €         Qsram cfg l1tcm                 Î               °okay            ³mediatek/mt8195/scp.img         Á   4        default            5           €   cros-ec-rpmsg             google,cros-ec-rpmsg            Ïcros-ec-rpmsg            clock-controller@10720000             mediatek,mt8195-scp_adsp            7    r                 V              6      dsp@10803000              mediatek,mt8195-dsp          7    €0            „               	  Qcfg sram          ,  c   "   X      "   n   "   Š   6       "   #      K  Tadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          ã   7           ñrx tx           ü   8   9        °okay            Á   :   ;                 mailbox@10816000              mediatek,mt8195-adsp-mbox           §            7    �`                       ¾                  8      mailbox@10817000              mediatek,mt8195-adsp-mbox           §            7    �p                       ¿                  9      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           7    ‰                    "        ã   7                  6                  <         	  audiosys          ”  c      !      !      "   Ú   "   Û   "   Ü   "   Ý   "   ß   "   g   "   "   "   #   "   n   "   e   "   a   "   b   "   c   "   d   #   2   6          ó  Tclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          °okay            (           H            Á   =                 serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           7                             �               c      #         	  Tbaud bus            °okay          serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           7                             Ž               c      #         	  Tbaud bus          	  °disabled          serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           7                             �               c      #         	  Tbaud bus          	  °disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           7                            Ó               c      #         	  Tbaud bus          	  °disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           7                            Ô               c      #         	  Tbaud bus          	  °disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           7                            Õ               c      #         	  Tbaud bus          	  °disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           7                      c   #           Tmain            Å           °okay               Ì      syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           7     0                V              2      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            7                              ¿               c   "   ™   "      #           Tparent-clk sel-clk spi-clk          °okay            default            >        i       ec@0                         +              google,cros-ec-spi          7            ±                 default            ?        } -ÆÀ         �   i2c-tunnel            google,cros-ec-i2c-tunnel           �                         +       sbs-battery@b             sbs,sbs-battery         7           ¯           Ã            regulator@0           google,cros-ec-regulator            7            þmt_pmic_vmc_ldo          O€        % 6î€           S      regulator@1           google,cros-ec-regulator            7           þmt_pmic_vmch_ldo             )2à        % 6î€           R      typec             google,cros-ec-typec                         +       connector@0           usb-c-connector         7            Ødual            ãhost            ísource        connector@1           usb-c-connector         7           Ødual            ãhost            ísource           keyboard-controller           google,cros-ec-keyb         ü                            P  9  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	 Ž + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i  ž ­t x c à á	 ä	 ¤  ø  q r s      4  F               	  	                        thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         7     °                        ©               c   #              #            [   @   A      $  glvts-calib-data-1 lvts-calib-data-2         x              Æ      svs@1100bc00              mediatek,mt8195-svs         7     ¼                        Ç               c   #           Tmain            [   B   @      (  gsvs-calibration-data t-calibration-data            #           svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           7     à                        Ë               ã   7           Ž           c   "   *   #   0        Tmain mm         °okay            default            C           É      pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           7     ð                                      Ž           c   "   +   #   N        Tmain mm       	  °disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            7                             À               c   "   ™   "      #   3        Tparent-clk sel-clk spi-clk        	  °disabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            7                             Á               c   "   ™   "      #   4        Tparent-clk sel-clk spi-clk        	  °disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            7    0                        Â               c   "   ™   "      #   5        Tparent-clk sel-clk spi-clk        	  °disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            7    €                        Ã               c   "   ™   "      #   <        Tparent-clk sel-clk spi-clk        	  °disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            7    �                        Ä               c   "   ™   "      #   =        Tparent-clk sel-clk spi-clk        	  °disabled          spi@1101d000              mediatek,mt8195-spi-slave           7    Ð                        Å               c   #   R        Tspi         Š   "           š   "   ˜      	  °disabled          spi@1101e000              mediatek,mt8195-spi-slave           7    à                        Æ               c   #   S        Tspi         Š   "           š   "   ˜      	  °disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           7           @                Ì               ™macirq        .  Taxi apb mac_main ptp_ref rmii_internal mac_cg         0  c   2       2      "   R   "   S   "   T   2           Š   "   R   "   S   "   T        š   "   Â   "   Ã   "   Ä        ã   7           ©   #        º   D        Ê   E        Ý   F        ð           û           	          	  °disabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           	           	#           	3                                    D      rx-queues-config            	=            	S           E   queue0           	d        	w          queue1           	d        	w          queue2           	d        	w          queue3           	d        	w             tx-queues-config            	�            	¥           F   queue0          	·            	d        	Ã          queue1          	·            	d        	Ã         queue2          	·            	d        	Ã         queue3          	·            	d        	Ã               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           7            -ÿ     >              	  Qmac ippc            Ì                     ?                      +                   €               c   #   /   "   í   #   B        Tsys_ck ref_ck mcu_ck            	Ñ   G      H            �        	Ö   I      g        °okay            	íhost            	õ   J   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          7                       Qmac                 �               Š   "   ,   "   -        š   "   –   "   –      $  c   #   /   "   í   !         #   B      $  Tsys_ck ref_ck mcu_ck dma_ck xhci_ck         °okay            
           
   K         mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          7    #             õ                         ƒ               c   "      #      #           Tsource hclk source_cg           °okay            
            
'         
9        
J L        �ëÂ          
Y         
h         
w         
         
…        default state_uhs              L        
“   M        
�   N        
©   O      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          7    $             Ç                         ‡               c   "      #      #   $        Tsource hclk source_cg           Š   "           š   "   ¿        °okay            
            
¶        
Ç      6           �ëÂ          
Ð         
w        default state_uhs              P   Q        
“   P         
×         
ä        
�   R        
©   S      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          7    %             æ                         ˆ               c   "       #      #   I        Tsource hclk source_cg           Š   "            š   "   ¿      	  °disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            7    '€                        ª               c   #              #           [   @   A      $  glvts-calib-data-1 lvts-calib-data-2         x              ½      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           7    )             )>              	  Qmac ippc                                  	Ñ   T           Š   "   .   "   /        š   "   –   "   –      $  c   2      "   ï   !         2         $  Tsys_ck ref_ck mcu_ck dma_ck xhci_ck         	Ö   I      h         �        °okay            
           	õ   J        
   K        
ò         usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           7    *       -ÿ    *>              	  Qmac ippc            Ì            *        ?                      +                                 Š   "   0        š   "   –        c   2      "   ñ   2           Tsys_ck ref_ck mcu_ck            	Ñ   U            �        	Ö   I      i        °okay            	íhost            	õ   J   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          7                       Qmac                               Š   "   1        š   "   –        c   2           Tsys_ck          °okay            
   K         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           7    +       -ÿ    +>              	  Qmac ippc            Ì            +        ?                      +                                 Š   "   2        š   "   –        c   2      "   ó   2   	        Tsys_ck ref_ck mcu_ck            	Ñ   V            �        	Ö   I      j        °okay            	íhost            	õ   J   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          7                       Qmac                               Š   "   3        š   "   –        c   2   	        Tsys_ck          °okay                     
   K         pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           +pci                      +           7    /        @       	  Qpcie-mac                                         ÿ      8  Ì�                           ‚                       à          "       W              ,          0  c   #   V   #   #   #   &   #   +   #   K   2         /  Tpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          Š   "   G        š   "           	Ñ   X      	  ;pcie-phy            ã   7            Þ           E                     `  X                  Y                      Y                     Y                     Y           °okay            default            Z   interrupt-controller                                  Þ              Y         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           +pci                      +           7    /€       @       	  Qpcie-mac                                         ÿ      8  Ì�       $       $           ‚       $       $       à          "       W              ,          (  c   #   W      #   X      #   Q   2         /  Tpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          Š   "   H        š   "           	Ñ   [         	  ;pcie-phy            ã   7           Þ           E                     `  X                  \                      \                     \                     \           °okay            default            ]   interrupt-controller                                  Þ              \         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         7    2À                       9               c   "   o   2      2           Tspi sf axi                       +            °okay            default            ^   flash@0           jedec,spi-nor           7            }u         f           w            efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            7    Á                              +      usb3-tx-imp@184,1           7  „           ˆ                  u      usb3-rx-imp@184,2           7  „           ˆ                 t      usb3-intr@185           7  …           ˆ                 s      usb3-tx-imp@186,1           7  †           ˆ                  r      usb3-rx-imp@186,2           7  †           ˆ                 q      usb3-intr@187           7  ‡           ˆ                 p      usb2-intr-p0@188,1          7  ˆ           ˆ             usb2-intr-p1@188,2          7  ˆ           ˆ            usb2-intr-p2@189,1          7  ‰           ˆ            usb2-intr-p3@189,2          7  ‰           ˆ            pciephy-rx-ln1@190,1            7  �           ˆ                  |      pciephy-tx-ln1-nmos@190,2           7  �           ˆ                 {      pciephy-tx-ln1-pmos@191,1           7  ‘           ˆ                  z      pciephy-rx-ln0@191,2            7  ‘           ˆ                 y      pciephy-tx-ln0-nmos@192,1           7  ’           ˆ                  x      pciephy-tx-ln0-pmos@192,2           7  ’           ˆ                 w      pciephy-glb-intr@193            7  “           ˆ                  v      dp-data@1ac         7  ¬              ´      lvts1-calib@1bc         7  ¼              @      lvts2-calib@1d0         7  Ð   8           A      svs-calib@580           7  €   d           B      socinfo-data1@7a0           7               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Ì        Ä             °okay       usb-phy@0           7               c   "   ò        Tref         �              U         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Ì        Å             °okay       usb-phy@0           7               c   "   ô        Tref         �              V         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         7    È                 c           mipi_tx0_pll            V            �          	  °disabled               ¢      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         7    É                 c           mipi_tx1_pll            V            �          	  °disabled               £      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          7    Ð             "€       €                š               j           c   _       #   ;      	  Tmain dma                         +            °okay            ] €        default            `      i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          7    Ð            "        €                ›               j           c   _      #   ;      	  Tmain dma                         +          	  °disabled          i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          7    Ð             "€       €                œ               j           c   _      #   ;      	  Tmain dma                         +            °okay            ] €        default            a   pmic@34         Þ             mediatek,mt6360         7   4                 ±      ‚           ™IRQB            default            b         �         clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          7    Ð0                V              _      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          7    à             " €       €                �               j           c   c       #   ;      	  Tmain dma                         +            °okay            ] €        default            d      i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          7    à            "        €                “               j           c   c      #   ;      	  Tmain dma                         +            °okay            ] €        ˜  0Ô        default            e   trackpad@15           elan,ekth3000           7           ±                 default            f        ²   g         �         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          7    à             "€       €                –               j           c   c      #   ;      	  Tmain dma                         +            °okay            ] €        default            h   codec@1a            7           ±      Y           ½           Î           Ý   i        é   j        ÷   k          realtek,rt5682s            ú                 amplifier@38              maxim,max98390          7   8              d           %Right           ½                     amplifier@39              maxim,max98390          7   9        %Left            ½                        i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          7    à0            "€       €                ˜               j           c   c      #   ;      	  Tmain dma                         +            °okay            ] €        default            l   tpm@50            google,cr50         7   P        ±      X           default            m         i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          7    à@            "        €                ™               j           c   c      #   ;      	  Tmain dma                         +            °okay            ] €        default            n   touchscreen@10            hid-over-i2c            7           7           ±      \           default            o        F   
        ]   g      	  °disabled          touchscreen@15            hid-over-i2c            7           7           ±      \           default            o        F   
        ]   g         clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          7    àP                V              c      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Ì        ã             ã   7           °okay       usb-phy@0           7               c   "   ð           Tref da_ref          �              T      usb-phy@700         7              c   !      "   ð        Tref da_ref          [   p   q   r        gintr rx_imp tx_imp          �              [         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           Ì        ä             °okay       usb-phy@0           7               c   "   î           Tref da_ref          �              G      usb-phy@700         7              c   !      "   î        Tref da_ref          [   s   t   u        gintr rx_imp tx_imp          �              H         phy@11e80000              mediatek,mt8195-pcie-phy            7    è                 Qsif         [   v   w   x   y   z   {   |      G  gglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          ã   7           �            °okay               X      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           7    ú        À         c            
  Tunipro mp           �          	  °disabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           7             @         c   }          0         �             Œ             ‹               ™job mmu gpu         h   ~      (  ã   7   
   7      7      7      7           |core0 core1 core2 core3 core4           °okay            �          clock-controller@13fbf000             mediatek,mt8195-mfgcfg          7    ûð                V              }      syscon@14000000           mediatek,mt8195-vppsys0 syscon          7                      V           ›                         %      dma-controller@14001000           mediatek,mt8195-mdp3-rdma           7                     ›                     ³              Ç   €        ã   7           Ô   �   €        c   %         <  ü                                                     Û         display@14002000              mediatek,mt8195-mdp3-fg         7                      ›                      c   %          display@14003000              mediatek,mt8195-mdp3-stitch         7     0                ›         0            c   %         display@14004000              mediatek,mt8195-mdp3-hdr            7     @                ›         @            c   %   "      display@14005000              mediatek,mt8195-mdp3-aal            7     P                       F               ›         P            c   %   
        ã   7         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           7     `                ›         `            ³    %        c   %         display@14007000              mediatek,mt8195-mdp3-tdshp          7     p                ›         p            c   %   #      display@14008000              mediatek,mt8195-mdp3-color          7     €                       I               ›         €            c   %   $        ã   7         display@14009000              mediatek,mt8195-mdp3-ovl            7     �                       J               ›         �            c   %   %        ã   7           Ô   �   ‚      display@1400a000              mediatek,mt8195-mdp3-padding            7                      ›                      c   %           ã   7         display@1400b000              mediatek,mt8195-mdp3-tcc            7     °                ›         °            c   %         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         7     À                ›         À            ³    +        c   %           Ô   �   ƒ        ã   7           Û         mutex@1400f000            mediatek,mt8195-vpp-mutex           7     ð                       P               ›         ð            c   %           ã   7         smi@14010000              mediatek,mt8195-smi-sub-common          7                     c   %      %      %           Tapb smi gals0           æ   ‚        ã   7              ƒ      smi@14011000              mediatek,mt8195-smi-sub-common          7                    c   %      %      %           Tapb smi gals0           æ   ‚        ã   7                     smi@14012000              mediatek,mt8195-smi-common-vpp          7                      c   %      %      %      %           Tapb smi gals0 gals1         ã   7              ‚      larb@14013000             mediatek,mt8195-smi-larb            7    0                ó           æ   ƒ        c   %      %           Tapb smi         ã   7              †      iommu@14018000            mediatek,mt8195-iommu-vpp           7    €              8     „   …   †   ‡   ˆ   ‰   Š   ‹   Œ   �   Ž   �   �   ‘               R               c   %           Tbclk            š           ã   7              �      clock-controller@14e00000             mediatek,mt8195-wpesys          7    à                 V              (      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         7    à                 V         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         7    à0                V         larb@14e04000             mediatek,mt8195-smi-larb            7    à@                ó           æ   ’        c   (      (           Tapb smi         ã   7              ¨      larb@14e05000             mediatek,mt8195-smi-larb            7    àP                ó           æ   ‚        c   (      (      %           Tapb smi gals            ã   7              ˆ      syscon@14f00000           mediatek,mt8195-vppsys1 syscon          7    ð                 V           ›      	                  '      mutex@14f01000            mediatek,mt8195-vpp-mutex           7    ð                       {               ›      	              c   '   '        ã   7         larb@14f02000             mediatek,mt8195-smi-larb            7    ð                 ó           æ   ’        c   '      '      %           Tapb smi gals            ã   7              §      larb@14f03000             mediatek,mt8195-smi-larb            7    ð0                ó           æ   ƒ        c   '      '      %           Tapb smi gals            ã   7              ‡      display@14f06000              mediatek,mt8195-mdp3-split          7    ð`                ›      	  `            c   '      '   +   '   ,        ã   7         display@14f07000              mediatek,mt8195-mdp3-tcc            7    ðp                ›      	  p            c   '         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           7    ð€                ›      	  €            ³  „  ¨        c   '           Ô   “            ã   7           Û         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           7    ð�                ›      	  �            ³  …  ©        c   '   
        Ô   “   ¤        ã   7           Û         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           7    ð                 ›      	               ³  †  ª        c   '           Ô   �   À        ã   7           Û         display@14f0b000              mediatek,mt8195-mdp3-fg         7    ð°                ›      	  °            c   '   	      display@14f0c000              mediatek,mt8195-mdp3-fg         7    ðÀ                ›      	  À            c   '         display@14f0d000              mediatek,mt8195-mdp3-fg         7    ðÐ                ›      	  Ð            c   '         display@14f0e000              mediatek,mt8195-mdp3-hdr            7    ðà                ›      	  à            c   '         display@14f0f000              mediatek,mt8195-mdp3-hdr            7    ðð                ›      	  ð            c   '         display@14f10000              mediatek,mt8195-mdp3-hdr            7    ñ                 ›      
               c   '          display@14f11000              mediatek,mt8195-mdp3-aal            7    ñ                       i               ›      
              c   '           ã   7         display@14f12000              mediatek,mt8195-mdp3-aal            7    ñ                        j               ›      
               c   '           ã   7         display@14f13000              mediatek,mt8195-mdp3-aal            7    ñ0                       k               ›      
  0            c   '   !        ã   7         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           7    ñ@                ›      
  @            ³  �  ¯        c   '         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           7    ñP                ›      
  P            ³  ‘  °        c   '   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           7    ñ`                ›      
  `            ³  ’  ±        c   '   %      display@14f17000              mediatek,mt8195-mdp3-tdshp          7    ñp                ›      
  p            c   '         display@14f18000              mediatek,mt8195-mdp3-tdshp          7    ñ€                ›      
  €            c   '   (      display@14f19000              mediatek,mt8195-mdp3-tdshp          7    ñ�                ›      
  �            c   '   )      display@14f1a000              mediatek,mt8195-mdp3-merge          7    ñ                 ›      
               c   '           ã   7         display@14f1b000              mediatek,mt8195-mdp3-merge          7    ñ°                ›      
  °            c   '           ã   7         display@14f1c000              mediatek,mt8195-mdp3-color          7    ñÀ                       t               ›      
  À            c   '           ã   7         display@14f1d000              mediatek,mt8195-mdp3-color          7    ñÐ                ›      
  Ð                   u               c   '           ã   7         display@14f1e000              mediatek,mt8195-mdp3-color          7    ñà                       v               ›      
  à            c   '           ã   7         display@14f1f000              mediatek,mt8195-mdp3-ovl            7    ñð                       w               ›      
  ð            c   '            ã   7           Ô   “   ¢      display@14f20000              mediatek,mt8195-mdp3-padding            7    ò                 ›                     c   '           ã   7         display@14f21000              mediatek,mt8195-mdp3-padding            7    ò                ›                    c   '           ã   7         display@14f22000              mediatek,mt8195-mdp3-padding            7    ò                 ›                     c   '           ã   7         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         7    ò0                ›        0            ³  Ÿ  «        c   '           Ô   “   £        ã   7           Û         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         7    ò@                ›        @            ³     ¬        c   '           Ô   “   ¦        ã   7           Û         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         7    òP                ›        P            ³  ¡  ­        c   '           Ô   �   Â        ã   7           Û         clock-controller@15000000             mediatek,mt8195-imgsys          7                      V              /      larb@15001000             mediatek,mt8195-smi-larb            7                     ó   	        æ   ”        c   /       /       /   
        Tapb smi gals            ã   7              ©      smi@15002000              mediatek,mt8195-smi-sub-common          7                      c   /      /      %           Tapb smi gals0           æ   ‚        ã   7              —      smi@15003000              mediatek,mt8195-smi-sub-common          7     0                c   /       /       /   
        Tapb smi gals0           æ   ’        ã   7              ”      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         7                     V              •      larb@15120000             mediatek,mt8195-smi-larb            7                     ó   
        æ   ”        c   /      •            Tapb smi         ã   7              ª      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          7                     V         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         7    "                 V              –      larb@15230000             mediatek,mt8195-smi-larb            7    #                 ó           æ   ”        c   /      –            Tapb smi         ã   7              «      clock-controller@15330000             mediatek,mt8195-ipesys          7    3                 V              0      larb@15340000             mediatek,mt8195-smi-larb            7    4                 ó           æ   —        c   0      0           Tapb smi         ã   7              ‰      clock-controller@16000000             mediatek,mt8195-camsys          7                      V              1      larb@16001000             mediatek,mt8195-smi-larb            7                     ó           æ   ˜        c   1       1       1           Tapb smi gals            ã   7              ¬      larb@16002000             mediatek,mt8195-smi-larb            7                      ó           æ   ™        c   1      1           Tapb smi         ã   7              Š      smi@16004000              mediatek,mt8195-smi-sub-common          7     @                c   1       1       1           Tapb smi gals0           æ   ’        ã   7              ˜      smi@16005000              mediatek,mt8195-smi-sub-common          7     P                c   1      1      %           Tapb smi gals0           æ   ‚        ã   7              ™      larb@16012000             mediatek,mt8195-smi-larb            7                     ó           æ   ™        c   š       š            Tapb smi         ã   7               ‹      larb@16013000             mediatek,mt8195-smi-larb            7    0                ó           æ   ˜        c   ›       ›            Tapb smi         ã   7               ­      larb@16014000             mediatek,mt8195-smi-larb            7    @                ó           æ   ™        c   œ       œ            Tapb smi         ã   7   !           ‘      larb@16015000             mediatek,mt8195-smi-larb            7    P                ó           æ   ˜        c   �       �            Tapb smi         ã   7   !           ²      clock-controller@1604f000             mediatek,mt8195-camsys_rawa         7    ð                V              š      clock-controller@1606f000             mediatek,mt8195-camsys_yuva         7    ð                V              ›      clock-controller@1608f000             mediatek,mt8195-camsys_rawb         7    ð                V              œ      clock-controller@160af000             mediatek,mt8195-camsys_yuvb         7    
ð                V              �      clock-controller@16140000             mediatek,mt8195-camsys_mraw         7                     V              ž      larb@16141000             mediatek,mt8195-smi-larb            7                    ó           æ   ˜        c   1       ž       1           Tapb smi gals            ã   7   "           ±      larb@16142000             mediatek,mt8195-smi-larb            7                     ó           æ   ™        c   ž       ž            Tapb smi         ã   7   "           �      clock-controller@17200000             mediatek,mt8195-ccusys          7                      V              Ÿ      larb@17201000             mediatek,mt8195-smi-larb            7                     ó           æ   ™        c   Ÿ       Ÿ            Tapb smi         ã   7              Œ      video-codec@18000000              mediatek,mt8195-vcodec-dec          Ç   €        Ô   “                        +            7                   @                Ì                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         7                       Ô   �  à   �  á         c   "   A   )      )      "   �        Tsel vdec lat top            Š   "   A        š   "   �        ã   7         video-codec@10000             mediatek,mtk-vcodec-lat         7                             Ä             0  Ô   “      “     “     “     “     “           c   "   A   )      )      "   �        Tsel vdec lat top            Š   "   A        š   "   �        ã   7         video-codec@25000             mediatek,mtk-vcodec-core            7     P                       Ã             P  Ô   “      “  ¡   “  ¢   “  £   “  ¤   “  ¥   “  ¦   “  §   “  ¨   “  ©         c   "   A   *      *      "   �        Tsel vdec lat top            Š   "   A        š   "   �        ã   7            larb@1800d000             mediatek,mt8195-smi-larb            7     Ð                ó           æ   ’        c   )       )            Tapb smi         ã   7              °      larb@1800e000             mediatek,mt8195-smi-larb            7     à                ó           æ            c   %      )            Tapb smi         ã   7              �      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         7     ð                V              )      larb@1802e000             mediatek,mt8195-smi-larb            7    à                ó           æ   ’        c   *       *            Tapb smi         ã   7              ¯      clock-controller@1802f000             mediatek,mt8195-vdecsys         7    ð                V              *      larb@1803e000             mediatek,mt8195-smi-larb            7    à                ó           æ            c   %      +            Tapb smi         ã   7              Ž      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           7    ð                V              +      clock-controller@190f3000             mediatek,mt8195-apusys_pll          7    0                V         clock-controller@1a000000             mediatek,mt8195-vencsys         7                      V              ,      larb@1a010000             mediatek,mt8195-smi-larb            7                     ó           æ   ’        c   ,      ,           Tapb smi         ã   7              ®      video-codec@1a020000              mediatek,mt8195-vcodec-enc          7                   H  Ô   “  `   “  a   “  b   “  c   “  d   “  v   “  w   “  x   “  y               U               Ç   €        c   ,         	  Tvenc_sel            Š   "   @        š   "   �        ã   7                        +         jpgdec-master             mediatek,mt8195-jpgdec          ã   7         0  Ô   “  m   “  n   “  r   “  s   “  t   “  u                     +            Ì   jpgdec@1a040000           mediatek,mt8195-jpgdec-hw           7                   0  Ô   “  m   “  n   “  r   “  s   “  t   “  u               W               c   ,           Tjpgdec          ã   7         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw           7                   0  Ô   “  m   “  n   “  r   “  s   “  t   “  u               X               c   ,           Tjpgdec          ã   7         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw           7                   0  Ô   �  �   �  Ž   �  ’   �  “   �  ”   �  •               \               c   -           Tjpgdec          ã   7            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           7                      V              -      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            7                     ü   ¡               V           ›   ¡                     &      jpgenc-master             mediatek,mt8195-jpgenc          ã   7            Ô   �  ‡   �  ˆ   �  ‰   �  Œ                     +            Ì   jpgenc@1a030000           mediatek,mt8195-jpgenc-hw           7                      Ô   “  g   “  h   “  i   “  l               V               c   ,           Tjpgenc          ã   7         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw           7                      Ô   �  ‡   �  ˆ   �  ‰   �  Œ               [               c   -           Tjpgenc          ã   7            larb@1b010000             mediatek,mt8195-smi-larb            7                     ó           æ   ‚        c   -      -      %            Tapb smi gals            ã   7              �      ovl@1c000000              mediatek,mt8195-disp-ovl            7                             |               ã   7           c   &            Ô   “           ›   ¡                rdma@1c002000             mediatek,mt8195-disp-rdma           7                             ~               ã   7           c   &           Ô   “            ›   ¡                color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           7     0                                      ã   7           c   &           ›   ¡     0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           7     @                       €               ã   7           c   &           ›   ¡     @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           7     P                       �               ã   7           c   &           ›   ¡     P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           7     `                       ‚               ã   7           c   &           ›   ¡     `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         7     p                       ƒ               ã   7           c   &   	        ›   ¡     p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         7     €                       „               ã   7           c   &      &   *   ¢        Tengine digital hs           	Ñ   ¢        ;dphy          	  °disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            7     �                       …               ã   7           c   &           ›   ¡     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         7                            Ž               ã   7           c   &      &   +   £        Tengine digital hs           	Ñ   £        ;dphy          	  °disabled          merge@1c014000            mediatek,mt8195-disp-merge          7    @                       �               ã   7           c   &           ›   ¡     @          dp-intf@1c015000              mediatek,mt8195-dp-intf         7    P                       ‘               c   &   ,   &      !           Tpixel engine pll            °okay       port       endpoint               ¤           ¶            mutex@1c016000            mediatek,mt8195-disp-mutex          7    `                       ’               ã   7           c   &           ›   ¡     `            ³  U      larb@1c018000             mediatek,mt8195-smi-larb            7    €                ó            æ   ’        c   &   (   &   (   %           Tapb smi gals            ã   7              ¥      larb@1c019000             mediatek,mt8195-smi-larb            7    �                ó           æ   ‚        c   &   (   %       %           Tapb smi gals            ã   7              „      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          7                     ü   ¡              ›   ¡                  V           D              .      smi@1c01b000              mediatek,mt8195-smi-common-vdo          7    °                 c   &   %   &   &   &   )   &   $        Tapb smi gals0 gals1         ã   7              ’      iommu@1c01f000            mediatek,mt8195-iommu-vdo           7    ð              8     ¥   ¦   §   ¨   ©   ª   «   ¬   ­   ®   ¯   °   ±   ²               �               š           c   &   '        Tbclk            ã   7              “      mutex@1c101000            mediatek,mt8195-disp-mutex          7                           î               ã   7           c   .           ›   ¡                 ³  À      larb@1c102000             mediatek,mt8195-smi-larb            7                     ó           æ   ’        c   .       .       .           Tapb smi gals            ã   7              ¦      larb@1c103000             mediatek,mt8195-smi-larb            7    0                ó           æ   ‚        c   .      .      %            Tapb smi gals            ã   7              …      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           7    @                       ï               c   .           ã   7           Ô   “   @        ›   ¡     @            Û         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           7    P                       ð               c   .           ã   7           Ô   �   `        ›   ¡     P            Û         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           7    `                       ñ               c   .           ã   7           Ô   “   A        ›   ¡     `            Û         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           7    p                       ò               c   .           ã   7           Ô   �   a        ›   ¡     p            Û         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           7    €                       ó               c   .           ã   7           Ô   “   B        ›   ¡     €            Û         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           7    �                       ô               c   .           ã   7           Ô   �   b        ›   ¡     �            Û         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           7                            õ               c   .           ã   7           Ô   “   C        ›   ¡                  Û         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           7    °                       ö               c   .           ã   7           Ô   �   c        ›   ¡     °            Û         vpp-merge@1c10c000            mediatek,mt8195-disp-merge          7    À                       ÷               c   .   	   .           Tmerge merge_async           ã   7           ›   ¡     À             #           .         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          7    Ð                       ø               c   .   
   .           Tmerge merge_async           ã   7           ›   ¡     Ð             #           .         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          7    à                       ù               c   .      .           Tmerge merge_async           ã   7           ›   ¡     à             #           .         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          7    ð                       ú               c   .      .           Tmerge merge_async           ã   7           ›   ¡     ð             #           .         vpp-merge@1c110000            mediatek,mt8195-disp-merge          7                            û               c   .      .           Tmerge merge_async           ã   7           ›   ¡                   7           .         dp-intf@1c113000              mediatek,mt8195-dp-intf         7    0                                      ã   7           c   .   /   .      !           Tpixel engine pll            °okay       port       endpoint               ³           ¼            hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  7    @            P            p            �                         °            À              4  Qmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  ›   ¡     @       ¡     P       ¡     p       ¡     �       ¡             ¡     °       ¡     À          h  c   .   %   .       .   #   .   !   .   $   .   "   .   1   .   &   .   '   .   (   .   )   .   *   "         ƒ  Tmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          ã   7           Ô   �   d   �   e                            (     .   3   .   4   .   5   .   6   .   7      E  vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx          7    P        €         [   ´        gdp_calibration_data         ã   7                  ¤               N  ¤        °okay            default            µ   ports                        +       port@0          7       endpoint               ¶           ¤         port@1          7      endpoint            _                        ·           º            aux-bus    panel         
    edp-panel           j   ¸        w   ¹   port       endpoint               º           ·                  dp-tx@1c600000            mediatek,mt8195-dp-tx           7    `        €         [   ´        gdp_calibration_data         ã   7                  Ê               N  ¤        °okay            ½            default            »              ports                        +       port@0          7       endpoint               ¼           ³         port@1          7      endpoint            _                               thermal-zones      cpu0-thermal            �  è        �   ú        ¥   ½      trips      trip-alert          µ L        Á  Ð         Epassive            ¾      trip-crit           µ †         Á  Ð      	   Ecritical             cooling-maps       map0            Ì   ¾      0  Ñ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            �  è        �   ú        ¥   ½      trips      trip-alert          µ L        Á  Ð         Epassive            ¿      trip-crit           µ †         Á  Ð      	   Ecritical             cooling-maps       map0            Ì   ¿      0  Ñ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            �  è        �   ú        ¥   ½      trips      trip-alert          µ L        Á  Ð         Epassive            À      trip-crit           µ †         Á  Ð      	   Ecritical             cooling-maps       map0            Ì   À      0  Ñ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            �  è        �   ú        ¥   ½      trips      trip-alert          µ L        Á  Ð         Epassive            Á      trip-crit           µ †         Á  Ð      	   Ecritical             cooling-maps       map0            Ì   Á      0  Ñ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            �  è        �   ú        ¥   ½       trips      trip-alert          µ L        Á  Ð         Epassive            Â      trip-crit           µ †         Á  Ð      	   Ecritical             cooling-maps       map0            Ì   Â      0  Ñ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            �  è        �   ú        ¥   ½      trips      trip-alert          µ L        Á  Ð         Epassive            Ã      trip-crit           µ †         Á  Ð      	   Ecritical             cooling-maps       map0            Ì   Ã      0  Ñ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            �  è        �   ú        ¥   ½      trips      trip-alert          µ L        Á  Ð         Epassive            Ä      trip-crit           µ †         Á  Ð      	   Ecritical             cooling-maps       map0            Ì   Ä      0  Ñ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            �  è        �   ú        ¥   ½      trips      trip-alert          µ L        Á  Ð         Epassive            Å      trip-crit           µ †         Á  Ð      	   Ecritical             cooling-maps       map0            Ì   Å      0  Ñ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            �  è        �   ú        ¥   Æ      trips      trip-alert          µ L        Á  Ð         Epassive       trip-crit           µ †         Á  Ð      	   Ecritical                vpu1-thermal            �  è        �   ú        ¥   Æ   	   trips      trip-alert          µ L        Á  Ð         Epassive       trip-crit           µ †         Á  Ð      	   Ecritical                gpu-thermal         �  è        �   ú        ¥   Æ   
   trips      trip-alert          µ L        Á  Ð         Epassive       trip-crit           µ †         Á  Ð      	   Ecritical                gpu1-thermal            �  è        �   ú        ¥   Æ      trips      trip-alert          µ L        Á  Ð         Epassive       trip-crit           µ †         Á  Ð      	   Ecritical                vdec-thermal            �  è        �   ú        ¥   Æ      trips      trip-alert          µ L        Á  Ð         Epassive       trip-crit           µ †         Á  Ð      	   Ecritical                img-thermal         �  è        �   ú        ¥   Æ      trips      trip-alert          µ L        Á  Ð         Epassive       trip-crit           µ †         Á  Ð      	   Ecritical                infra-thermal           �  è        �   ú        ¥   Æ      trips      trip-alert          µ L        Á  Ð         Epassive       trip-crit           µ †         Á  Ð      	   Ecritical                cam0-thermal            �  è        �   ú        ¥   Æ      trips      trip-alert          µ L        Á  Ð         Epassive       trip-crit           µ †         Á  Ð      	   Ecritical                cam1-thermal            �  è        �   ú        ¥   Æ      trips      trip-alert          µ L        Á  Ð         Epassive       trip-crit           µ †         Á  Ð      	   Ecritical                soc-area-thermal            �  è        �   ú        ¥   Ç   trips      trip-crit           µ H         Á  è      	   Ecritical                pmic-area-thermal           �  è        �            ¥   È   trips      trip-crit           µ H         Á  è      	   Ecritical                   backlight-lcd0            pwm-backlight           à      ÿ        ò  @              R              ÿ        /   É     ¡         j   Ê           ¹      chosen          4serial0:115200n8          memory@40000000         +memory          7    @       €         regulator-pp3300-disp-x           regulator-fixed         þpp3300_disp_x            2Z         % 2Z         =  	Ä         @        S      7            default            Ë        X   j           ¸      regulator-pp3300-ldo-z5           regulator-fixed         þpp3300_ldo_z5            Y         c         2Z         % 2Z         X   Ê           k      regulator-pp3300-s3           regulator-fixed       
  þpp3300_s3            Y         c         2Z         % 2Z         X   j           g      regulator-pp3300-z2           regulator-fixed       
  þpp3300_z2            Y         c         2Z         % 2Z         X   Ê           j      regulator-pp4200-z2           regulator-fixed       
  þpp4200_z2            Y         c         @@        % @@        X   Ê      regulator-pp5000-s5           regulator-fixed       
  þpp5000_s5            Y         c         LK@        % LK@        X   Ê      regulator-ppvar-sys           regulator-fixed       
  þppvar_sys            Y         c           Ê      thermal-sensor-t1             generic-adc-thermal         x            u   Ì            �sensor-channel        à  ’ÿÿØð  ÿÿìx  Í      ~  ˆ  %  '  Ã  :˜  [  N   ï  a¨  „  u0    ˆ¸  ¹  œ@  ]  ¯È    ÃP  Á  ÖØ  €  ê`  G  ýè   p   í $ø   Ê 8€   ¬ L   “ _�   } s   k †    \ š(   O ­°   D Á8   ; ÔÀ   3 èH   ,           Ç      thermal-sensor-t2             generic-adc-thermal         x            u   Ì           �sensor-channel        à  ’ÿÿØð  ÿÿìx  Í      ~  ˆ  %  '  Ã  :˜  [  N   ï  a¨  „  u0    ˆ¸  ¹  œ@  ]  ¯È    ÃP  Á  ÖØ  €  ê`  G  ýè   p   í $ø   Ê 8€   ¬ L   “ _�   } s   k †    \ š(   O ­°   D Á8   ; ÔÀ   3 èH   ,           È      regulator-5v0-usb-vbus            regulator-fixed       	  þusb-vbus             LK@        % LK@         @         Y           K      reserved-memory                      +            Ì   memory@50000000           shared-dma-pool         7    P       �           «           4      memory@60000000           shared-dma-pool         7    `        Ø           «           ;      memory@60d80000           shared-dma-pool         7    `Ø                  «           =      memory@60e80000           shared-dma-pool         7    `è       (           «           :         rt1019p           realtek,rt1019p         ²rt1019p         ½            default            Í        ¸      d          	  °disabled             	compatible interrupt-parent #address-cells #size-cells model chassis-type dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c7 mmc0 mmc1 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform mediatek,adsp mediatek,dai-link pinctrl-names pinctrl-0 audio-routing link-name mediatek,clk-provider sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit gpio-line-names pinmux input-enable bias-pull-up bias-disable drive-strength-microamp drive-strength bias-pull-down output-high output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells firmware-name memory-region mediatek,rpmsg-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names mediatek,etdm-in2-cowork-source mediatek,etdm-out2-cowork-source mediatek,pad-select spi-max-frequency wakeup-source google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup dr_mode vusb33-supply rx-fifo-depth vbus-supply bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable pinctrl-1 vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 mediatek,u3p-dis-msk usb2-lpm-disable bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-rx-bus-width spi-tx-bus-width bits #phy-cells i2c-scl-internal-delay-ns vcc-supply #sound-dai-cells realtek,jd-src AVDD-supply MICVDD-supply VBAT-supply realtek,amic-delay-ms reset-gpios sound-name-prefix hid-descr-addr post-power-on-delay-ms vdd-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz data-lanes power-supply backlight polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device brightness-levels default-brightness-level enable-gpios num-interpolated-steps pwms stdout-path enable-active-high gpio vin-supply regulator-boot-on io-channels io-channel-names temperature-lookup-table no-map label sdb-gpios 