Ðþí s"   8 d¤   (            ~ dl                             1    google,tomato-rev1 google,tomato mediatek,mt8195                                     +            7Acer Tomato (rev1) board       aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          ƒ/soc/vpp-merge@1c10f000          Š/soc/vpp-merge@1c110000          ‘/soc/dma-controller@1c104000             œ/soc/dma-controller@1c105000             §/soc/dma-controller@1c106000             ²/soc/dma-controller@1c107000             ½/soc/dma-controller@1c108000             È/soc/dma-controller@1c109000             Ó/soc/dma-controller@1c10a000             Þ/soc/dma-controller@1c10b000             é/soc/i2c@11e00000            î/soc/i2c@11e01000            ó/soc/i2c@11e02000            ø/soc/i2c@11e03000            ý/soc/i2c@11e04000           /soc/i2c@11d00000           /soc/i2c@11d02000           /soc/mmc@11230000           /soc/mmc@11240000           /soc/serial@11001100          cpus                         +       cpu@0           cpu           arm,cortex-a55          *            .psci            <               Pec3@        `  4        s              ƒ  €         �   @        ¢   €        ¯  €         ¼   @        Î   €        Û           ì           û                    cpu@100         cpu           arm,cortex-a55          *           .psci            <               Pec3@        `  4        s              ƒ  €         �   @        ¢   €        ¯  €         ¼   @        Î   €        Û           ì           û                    cpu@200         cpu           arm,cortex-a55          *           .psci            <               Pec3@        `  4        s              ƒ  €         �   @        ¢   €        ¯  €         ¼   @        Î   €        Û           ì           û                    cpu@300         cpu           arm,cortex-a55          *           .psci            <               Pec3@        `  4        s              ƒ  €         �   @        ¢   €        ¯  €         ¼   @        Î   €        Û           ì           û                    cpu@400         cpu           arm,cortex-a78          *           .psci            <              P�fÔÀ        `           s              ƒ           �   @        ¢           ¯           ¼   @        Î           Û   	        ì           û   
                 cpu@500         cpu           arm,cortex-a78          *           .psci            <              P�fÔÀ        `           s              ƒ           �   @        ¢           ¯           ¼   @        Î           Û   	        ì           û   
                 cpu@600         cpu           arm,cortex-a78          *           .psci            <              P�fÔÀ        `           s              ƒ           �   @        ¢           ¯           ¼   @        Î           Û   	        ì           û   
                 cpu@700         cpu           arm,cortex-a78          *           .psci            <              P�fÔÀ        `           s              ƒ           �   @        ¢           ¯           ¼   @        Î           Û   	        ì           û   
                 cpu-map    cluster0       core0                    core1                    core2                    core3                    core4                    core5                    core6                    core7                          idle-states         psci       cpu-retention-l           arm,idle-state                     6        G   2        X   _        h  D                 cpu-retention-b           arm,idle-state                     6        G   -        X   Œ        h  ä                 cpu-off-l             arm,idle-state                    6        G   7        X   ›        h  H                 cpu-off-b             arm,idle-state                    6        G   2        X   È        h  è                    l2-cache0             cache           y           …           ’   @        ¤           Û            …                 l2-cache1             cache           y           …           ’   @        ¤           Û            …           	      l3-cache              cache           y           …            ’   @        ¤            …                    dsu-pmu           arm,dsu-pmu         “                       ž                                £fail          dmic-codec            dmic-codec          ª           ·   2      mt8195-sound            Ç           £okay            Ù         }  çDL10_FE DPTX_BE ETDM1_IN_BE ETDM2_IN_BE ETDM1_OUT_BE ETDM2_OUT_BE UL_SRC1_BE AFE_SOF_DL2 AFE_SOF_DL3 AFE_SOF_UL4 AFE_SOF_UL5            ùdefault                  ?  Headphone HPOL Headphone HPOR IN1P Headset Mic Ext Spk Speaker        %    mediatek,mt8195_mt6359_rt1019_rt5682             7mt8195_r1019_5682      mm-dai-link         ETDM1_IN_BE         )cpu       hs-playback-dai-link            ETDM1_OUT_BE            )cpu    codec           ?                hs-capture-dai-link         ETDM2_IN_BE         )cpu    codec           ?                spk-playback-dai-link           ETDM2_OUT_BE            )cpu    codec           ?            displayport-dai-link            DPTX_BE    codec           ?               fixed-factor-clock-13m            fixed-factor-clock          I            V           ]           g           rclk13m             2      oscillator-26m            fixed-clock         I            PŒº€        rclk26m                   oscillator-32k            fixed-clock         I            P  €         rclk32k        performance-controller@11bc10             mediatek,cpufreq-hw          *     ¼            ½0               …                    opp-table-gpu             operating-points-v2          Ÿ           |   opp-390000000           ª    >í€        ± 	‰h      opp-410000000           ª    p€        ± 	¡Ò      opp-431000000           ª    °‰À        ± 	¡Ò      opp-473000000           ª    1h@        ± 	º<      opp-515000000           ª    ²FÀ        ± 	º<      opp-556000000           ª    !#ã         ± 	Ò¦      opp-598000000           ª    #¤Á€        ± 	ë      opp-640000000           ª    &%          ± 	ë      opp-670000000           ª    'ïc€        ± 
ä      opp-700000000           ª    )¹'         ± 
L¸      opp-730000000           ª    +‚ê€        ± 
}Œ      opp-760000000           ª    -L®         ± 
®`      opp-790000000           ª    /q€        ± 
ß4      opp-820000000           ª    0à5         ±       opp-850000000           ª    2©ø€        ± @Ü      opp-880000000           ª    4s¼         ± q°         pmu-a55           arm,cortex-a55-pmu                      “                  pmu-a78           arm,cortex-a78-pmu                      “                  psci              arm,psci-1.0            5smc       timer             arm,armv8-timer                   @  “                                             
             soc                      +             simple-bus           ¿        Æ                          interrupt-controller@c000000              arm,gic-v3          Ñ           â                        ù         *                                    “      	                              ppi-partitions     interrupt-partition-0           .                             interrupt-partition-1           .                                   syscon@10000000            mediatek,mt8195-topckgen syscon         *                      I              !      syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          *                     I           7              "      syscon@10003000           mediatek,mt8195-pericfg syscon          *     0                I              H      pinctrl@10005000              mediatek,mt8195-pinctrl       €  *     P            Ñ             Ó             Ô             â             ë             ô              °              B  Diocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            N        ^           j              �         ù        “       ë               Ñ            v        ùdefault                 >  šI2S_SPKR_MCLK I2S_SPKR_DATAIN I2S_SPKR_LRCK I2S_SPKR_BCLK EC_AP_INT_ODL AP_FLASH_WP_L TCHPAD_INT_ODL EDP_HPD_1V8 AP_I2C_CAM_SDA AP_I2C_CAM_SCL AP_I2C_TCHPAD_SDA_1V8 AP_I2C_TCHPAD_SCL_1V8 AP_I2C_AUD_SDA AP_I2C_AUD_SCL AP_I2C_TPM_SDA_1V8 AP_I2C_TPM_SCL_1V8 AP_I2C_TCHSCR_SDA_1V8 AP_I2C_TCHSCR_SCL_1V8 EC_AP_HPD_OD  PCIE_NVME_RST_L PCIE_NVME_CLKREQ_ODL PCIE_RST_1V8_L PCIE_CLKREQ_1V8_ODL PCIE_WAKE_1V8_ODL CLK_24M_CAM0 CAM1_SEN_EN AP_I2C_PWR_SCL_1V8 AP_I2C_PWR_SDA_1V8 AP_I2C_MISC_SCL AP_I2C_MISC_SDA EN_PP5000_HDMI_X AP_HDMITX_HTPLG  AP_HDMITX_SCL_1V8 AP_HDMITX_SDA_1V8 AP_RTC_CLK32K AP_EC_WATCHDOG_L SRCLKENA0 SRCLKENA1 PWRAP_SPI0_CS_L PWRAP_SPI0_CK PWRAP_SPI0_MOSI PWRAP_SPI0_MISO SPMI_SCL SPMI_SDA    I2S_HP_DATAIN I2S_HP_MCLK I2S_HP_BCK I2S_HP_LRCK I2S_HP_DATAOUT SD_CD_ODL EN_PP3300_DISP_X TCHSCR_RST_1V8_L TCHSCR_REPORT_DISABLE EN_PP3300_WLAN_X BT_KILL_1V8_L I2S_SPKR_DATAOUT WIFI_KILL_1V8_L BEEP_ON SCP_I2C_SENSOR_SCL_1V8 SCP_I2C_SENSOR_SDA_1V8     AUD_CLK_MOSI AUD_SYNC_MOSI AUD_DAT_MOSI0 AUD_DAT_MOSI1 AUD_DAT_MISO0 AUD_DAT_MISO1 AUD_DAT_MISO2 SCP_VREQ_VAO AP_SPI_GSC_TPM_CLK AP_SPI_GSC_TPM_MOSI AP_SPI_GSC_TPM_CS_L AP_SPI_GSC_TPM_MISO EN_PP1000_CAM_X AP_EDP_BKLTEN  USB3_HUB_RST_L  WLAN_ALERT_ODL EC_IN_RW_ODL GSC_AP_INT_ODL HP_INT_ODL CAM0_RST_L CAM1_RST_L TCHSCR_INT_1V8_L CAM1_DET_L RST_ALC1011_L   BL_PWM_1V8 UART_AP_TX_DBG_RX UART_DBG_TX_AP_RX EN_SPKR AP_EC_WARM_RST_REQ UART_SCP_TX_DBGCON_RX UART_DBGCON_TX_SCP_RX   KPCOL0  MT6315_GPU_INT MT6315_PROC_BC_INT SD_CMD SD_CLK SD_DAT0 SD_DAT1 SD_DAT2 SD_DAT3 EMMC_DAT7 EMMC_DAT6 EMMC_DAT5 EMMC_DAT4 EMMC_RSTB EMMC_CMD EMMC_CLK EMMC_DAT3 EMMC_DAT2 EMMC_DAT1 EMMC_DAT0 EMMC_DSL   MT6360_INT_ODL SCP_JTAG0_TRSTN AP_SPI_EC_CS_L AP_SPI_EC_CLK AP_SPI_EC_MOSI AP_SPI_EC_MISO SCP_JTAG0_TMS SCP_JTAG0_TCK SCP_JTAG0_TDO SCP_JTAG0_TDI AP_SPI_FLASH_CS_L AP_SPI_FLASH_CLK AP_SPI_FLASH_MOSI AP_SPI_FLASH_MISO                 audio-default-pins                pins-cmd-dat          D  ª  E  F  G  H  I  J  K           <  1  2  3  4  5      pins-hp-jack-int-odl            ª  Y          ±        ¾   e         cr50-irq-default-pins              k   pins-gsc-ap-int-odl         ª  X          ±         cros-ec-irq-default-pins               >   pins-ec-ap-int-odl          ª           ¾   e         ±         edptx-default-pins             ³   pins-cmd-dat            ª           ¾         disp-pwm0-default-pins             B   pins-disp-pwm           ª  R   a         dptx-default-pins              ¹   pins-cmd-dat            ª           ¾         i2c0-default-pins              b   pins-bus            ª    	         Ë        Ø  è         i2c1-default-pins              c   pins-bus            ª  
          ¾  è        Ø  è         i2c2-default-pins              f   pins-bus            ª             Ë        Ø  è         i2c3-default-pins              j   pins-bus            ª            ¾  è        Ø  è         i2c4-default-pins              l   pins-bus            ª            ¾  è        ð            i2c5-default-pins              ^   pins-bus            ª             Ë        Ø  è         i2c7-default-pins              _   pins-bus            ª             Ë         mmc0-default-pins              K   pins-cmd-dat          $  ª  ~  }  |  {  w  v  u  t  y         ±        ð           ¾   e      pins-clk            ª  z        ð           ÿ   f      pins-rst            ª  x        ð           ¾   e         mmc0-uhs-pins              L   pins-cmd-dat          $  ª  ~  }  |  {  w  v  u  t  y         ±        ð           ¾   e      pins-clk            ª  z        ð           ÿ   f      pins-ds         ª          ð           ÿ   f      pins-rst            ª  x        ð           ¾   e         mmc1-detect-pins               P   pins-insert         ª  6          ¾         mmc1-default-pins              O   pins-cmd-dat            ª  n  p  q  r  s         ±        ð           ¾   e      pins-clk            ª  o        ð           ÿ   f         nor-default-pins               \   pins-ck-io          ª  Ž  �  �        ð            ÿ      pins-cs         ª  Œ        ð            ¾         pcie0-default-pins     pins-bus            ª               ¾         pcie1-default-pins             [   pins-bus            ª               ¾         panel-pwr-default-pins             É   pins-vreg-en            ª  7          pio-default-pins                  pins-wifi-enable            ª  :                  ð         pins-low-power-pd         ,  ª        .   /   0   A   B   C   D   €   �          ±         ÿ      pins-low-power-pupd       <  ª  M   N   O   P   S   U   Z   [   ]   ^   _   `   h   i   k          ±        ÿ   e         rt1019p-default-pins               Ë   pins-amp-sdb            ª  d                   scp-default-pins               4   pins-vreq           ª  L         Ë         ±         spi0-default-pins              =   pins-cs-mosi-clk            ª  „  †  …         Ë      pins-miso           ª  ‡         ÿ         subpmic-default-pins               `   pins-subpmic-int-n          ª  ‚          ±         ¾         trackpad-default-pins              d   pins-int-n          ª            ±         ¾         touchscreen-default-pins               m   pins-int-n          ª  \          ±        ¾   e      pins-rst            ª  8                pins-report-sw          ª  9                      syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            *     `           power-controller          !    mediatek,mt8195-power-controller                         +            %              6   power-domain@8          *                        +            %           9      power-domain@9          *   	        V          !           Gmfg alt         S   "                     +            %           9   #   power-domain@10         *   
        %          power-domain@11         *           %          power-domain@12         *           %          power-domain@13         *           %          power-domain@14         *           %                power-domain@15         *         Ø  V   !      !      !      !   	   !   @   !   A   !   K   !   à   $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $      $           Gvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           S   "                     +            %      power-domain@16         *         8  V   !   â   %   $   %   %   %   &   %   '   %   (   %   )      D  Gvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         S   "                     +            %      power-domain@17         *           V   !   á   &      &           Gvppsys1 vppsys1-0 vppsys1-1         S   "        %          power-domain@22         *            V   '      '      '      '         $  Gwepsys-0 wepsys-1 wepsys-2 wepsys-3         S   "        %          power-domain@23         *           V   (            Gvdec0-0         S   "                     +            %       power-domain@24         *           V   )            Gvdec1-0         S   "        %          power-domain@25         *           V   *            Gvdec2-0         S   "        %             power-domain@26         *           V   +            Gvenc0-larb          S   "                     +            %       power-domain@27         *           V   ,            Gvenc1-larb          S   "        %             power-domain@18         *            V   !   ã   -       -      -         &  Gvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           S   "                     +            %      power-domain@19         *           S   "        %          power-domain@20         *           S   "        %          power-domain@21         *           V   !   Q        Ghdmi_tx         %             power-domain@28         *           V   .       .   
        Gimg-0 img-1         S   "                     +            %      power-domain@29         *           %          power-domain@30         *           V   !      .      /           Gipe ipe-0 ipe-1         S   "        %             power-domain@31         *         (  V   0       0      0      0      0           Gcam-0 cam-1 cam-2 cam-3 cam-4           S   "                     +            %      power-domain@32         *            %          power-domain@33         *   !        %          power-domain@34         *   "        %                   power-domain@0          *            S   "        %          power-domain@1          *           S   "        %          power-domain@2          *           %          power-domain@3          *           %          power-domain@4          *           V   !   5   !   7        Gcsi_rx_top csi_rx_top1          %          power-domain@5          *           V   1           Gether           %          power-domain@6          *           V   !   X   !   n        Gadsp adsp1                       +            S   "        %      power-domain@7          *            V   !   g   !   "   !   n   "   2        Gaudio audio1 audio2 audio3          S   "        %                   watchdog@10007000             mediatek,mt8195-wdt         *     p                7              ;      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           *     À                I                     timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         *    p                “      	               V   2      pwrap@10024000            mediatek,mt8195-pwrap syscon            *    @                Dpwrap           “       ó               V   "      "          	  Gspi wrap            e   !   $        u   !   Ë   pmic              mediatek,mt6359          ù        Ñ           Œ      Þ      adc           mediatek,mt6359-auxadc                    mt6359codec         ²           Å         regulators            mediatek,mt6359-regulator      buck_vs1            Ùvs1         è 5           !‘À                     4      buck_vgpu11         Ùvgpu11          è €          7        H  ˆ           È        ]                   4      buck_vmodem         Ùvmodem          è €          Èà        H  *           È      buck_vpu            Ùvpu         è €          7        H  ˆ           È        ]                   4      buck_vcore          Ùvcore           è €          Ö         H  ˆ           È        ]                   4                 buck_vs2            Ùvs2         è 5           j                      4      buck_vpa            Ùvpa         è ¡           7±Ð          ,      buck_vproc2         Ùvproc2          è €          7        H  L           È        ]                buck_vproc1         Ùvproc1          è €          7        H  L           È        ]                buck_vcore_sshub            Ùvcore_sshub         è €          7      buck_vgpu11_sshub           Ùvgpu11_sshub            è dp          dp         4      ldo_vaud18          Ùvaud18          è w@          w@           ð      ldo_vsim1           Ùvsim1           è ð           /M`      ldo_vibr            Ùvibr            è O€          2Z       ldo_vrf12           Ùvrf12           è Èà          Ö          4      ldo_vusb            Ùvusb            è -ÆÀ          -ÆÀ          À         4           I      ldo_vsram_proc2         Ùvsram_proc2         è ¡           ½¶        H  L           ð         4      ldo_vio18           Ùvio18           è ð           ýà          À         4           g      ldo_vcamio          Ùvcamio          è ð           ýà      ldo_vcn18           Ùvcn18           è w@          w@           ð      ldo_vfe28           Ùvfe28           è *¹€          *¹€           x      ldo_vcn13           Ùvcn13           è »           Ö       ldo_vcn33_1_bt          Ùvcn33_1_bt          è *¹€          5gà      ldo_vcn33_1_wifi            Ùvcn33_1_wifi            è *¹€          5gà      ldo_vaux18          Ùvaux18          è w@          w@           ð         4      ldo_vsram_others            Ùvsram_others            è q°          q°        H  ˆ           ð           #      ldo_vefuse          Ùvefuse          è ð           „€      ldo_vxo22           Ùvxo22           è w@          !‘À         4      ldo_vrfck           Ùvrfck           è ã`          ð       ldo_vrfck_1         Ùvrfck           è ëÀ          j       ldo_vbif28          Ùvbif28          è *¹€          *¹€           ð      ldo_vio28           Ùvio28           è *¹€          2Z          4      ldo_vemc            Ùvemc            è ,@           2Z       ldo_vemc_1          Ùvemc            è &%           2Z            M      ldo_vcn33_2_bt          Ùvcn33_2_bt          è *¹€          5gà      ldo_vcn33_2_wifi            Ùvcn33_2_wifi            è *¹€          5gà      ldo_va12            Ùva12            è O€          Ö          4      ldo_va09            Ùva09            è 5           O€      ldo_vrf18           Ùvrf18           è ð           žP      ldo_vsram_md          	  Ùvsram_md            è ¡           ½¶        H  *           ð      ldo_vufs            Ùvufs            è ð           ýà         4           N      ldo_vm18            Ùvm18            è ð           ýà         4      ldo_vbbck           Ùvbbck           è Èà          O€      ldo_vsram_proc1         Ùvsram_proc1         è ¡           ½¶        H  L           ð         4      ldo_vsim2           Ùvsim2           è ð           /M`      ldo_vsram_others_sshub          Ùvsram_others_sshub          è ¡           ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             *    p            �                Dpmif spmimst            V   "      "       !   E      (  Gpmif_sys_ck pmif_tmr_ck spmimst_clk_mux         e   !   $        u   !   Ë                     +       mt6315@6              mediatek,mt6315-regulator           *          regulators     vbuck1          ÙVbcpu           è €          7                   H  j        ]                   4           
            mt6315@7              mediatek,mt6315-regulator           *          regulators     vbuck1          ÙVgpu            è €          7                   H  j        ]                                    infra-iommu@10315000              mediatek,mt8195-iommu-infra         *    1P       P       P  “                                                                         u              V      mailbox@10320000              mediatek,mt8195-gce         *    2        @         “       â               ‚           V   "              Ÿ      mailbox@10330000              mediatek,mt8195-gce         *    3        @         “       ä               ‚           V   "              }      scp@10500000              mediatek,mt8195-scp       0  *    P             r             p        €         Dsram cfg l1tcm          “      Î               £okay            Žmediatek/mt8195/scp.img         œ   3        ùdefault            4           ~   cros-ec-rpmsg             google,cros-ec-rpmsg            ªcros-ec-rpmsg            clock-controller@10720000             mediatek,mt8195-scp_adsp            *    r                 I              5      dsp@10803000              mediatek,mt8195-dsp          *    €0            „               	  Dcfg sram          ,  V   !   X      !   n   !   Š   5       !   #      K  Gadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          ¾   6           Ìrx tx           ×   7   8        £okay            œ   9   :                 mailbox@10816000              mediatek,mt8195-adsp-mbox           ‚            *    �`                “      ¾                  7      mailbox@10817000              mediatek,mt8195-adsp-mbox           ‚            *    �p                “      ¿                  8      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           *    ‰                 Þ   !        ¾   6           “      6               ð   ;         	  ÷audiosys          ”  V                    !   Ú   !   Û   !   Ü   !   Ý   !   ß   !   g   !   "   !   #   !   n   !   e   !   a   !   b   !   c   !   d   "   2   5          ó  Gclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp          £okay                       #            œ   <                 serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                     “       �               V      "         	  Gbaud bus            £okay          serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                     “       Ž               V      "         	  Gbaud bus          	  £disabled          serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                     “       �               V      "         	  Gbaud bus          	  £disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                     “      Ó               V      "         	  Gbaud bus          	  £disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                     “      Ô               V      "         	  Gbaud bus          	  £disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           *                     “      Õ               V      "         	  Gbaud bus          	  £disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           *                      V   "           Gmain                        £okay               Ê      syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           *     0                I              1      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *                      “       ¿               V   !   ™   !      "           Gparent-clk sel-clk spi-clk          £okay            ùdefault            =        D       ec@0                         +              google,cros-ec-spi          *            Œ                 ùdefault            >        X -ÆÀ         j   i2c-tunnel            google,cros-ec-i2c-tunnel           x                         +       sbs-battery@b             sbs,sbs-battery         *           Š           ž            regulator@0           google,cros-ec-regulator            *            Ùmt_pmic_vmc_ldo         è O€          6î€           R      regulator@1           google,cros-ec-regulator            *           Ùmt_pmic_vmch_ldo            è )2à          6î€           Q      typec             google,cros-ec-typec                         +       connector@0           usb-c-connector         *            ³dual            ¾host            Èsource        connector@1           usb-c-connector         *           ³dual            ¾host            Èsource           keyboard-controller           google,cros-ec-keyb         ×           ç            ú     D    ž ­t x c à á	 q	 r  s  }  0  Y  1   
 d  " # (  \       V 
 |  } )   	 Ž + ^  a    !  % $ '	 &
 +  , . / - 3 2 * 5	 4 9     	  	 

 8 l j       6 	  g i      4  !               	  	                        thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         *     °                “       ©               V   "           ð   "            6   ?   @      $  Blvts-calib-data-1 lvts-calib-data-2         S              Ä      svs@1100bc00              mediatek,mt8195-svs         *     ¼                “       Ç               V   "           Gmain            6   A   ?      (  Bsvs-calibration-data t-calibration-data         ð   "           ÷svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           *     à                “       Ë               ¾   6           i           V   !   *   "   0        Gmain mm         £okay            ùdefault            B           Ç      pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           *     ð                “                     i           V   !   +   "   N        Gmain mm       	  £disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *                     “       À               V   !   ™   !      "   3        Gparent-clk sel-clk spi-clk        	  £disabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *                     “       Á               V   !   ™   !      "   4        Gparent-clk sel-clk spi-clk        	  £disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *    0                “       Â               V   !   ™   !      "   5        Gparent-clk sel-clk spi-clk        	  £disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *    €                “       Ã               V   !   ™   !      "   <        Gparent-clk sel-clk spi-clk        	  £disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            *    �                “       Ä               V   !   ™   !      "   =        Gparent-clk sel-clk spi-clk        	  £disabled          spi@1101d000              mediatek,mt8195-spi-slave           *    Ð                “       Å               V   "   R        Gspi         e   !           u   !   ˜      	  £disabled          spi@1101e000              mediatek,mt8195-spi-slave           *    à                “       Æ               V   "   S        Gspi         e   !           u   !   ˜      	  £disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           *           @         “      Ì               tmacirq        .  Gaxi apb mac_main ptp_ref rmii_internal mac_cg         0  V   1       1      !   R   !   S   !   T   1           e   !   R   !   S   !   T        u   !   Â   !   Ã   !   Ä        ¾   6           „   "        •   C        ¥   D        ¸   E        Ë           Ö           á          	  £disabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           î           þ           	                                    C      rx-queues-config            	            	.           D   queue0           	?        	R          queue1           	?        	R          queue2           	?        	R          queue3           	?        	R             tx-queues-config            	j            	€           E   queue0          	’            	?        	ž          queue1          	’            	?        	ž         queue2          	’            	?        	ž         queue3          	’            	?        	ž               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           *            -ÿ     >              	  Dmac ippc            ¿                     ?                      +           “       €               V   "   /   !   í   "   B        Gsys_ck ref_ck mcu_ck            	¬   F      G            j        	±   H      g        £okay            	Èhost            	Ð   I   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          *                       Dmac         “       �               e   !   ,   !   -        u   !   –   !   –      $  V   "   /   !   í             "   B      $  Gsys_ck ref_ck mcu_ck dma_ck xhci_ck         £okay            	Þ           	ì   J         mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          *    #             õ                 “       ƒ               V   !      "      "           Gsource hclk source_cg           £okay            	ø            
         
        
% L        \ëÂ          
4         
C         
R         
Z         
`        ùdefault state_uhs              K        
n   L        
x   M        
„   N      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          *    $             Ç                 “       ‡               V   !      "      "   $        Gsource hclk source_cg           e   !           u   !   ¿        £okay            	ø            
‘        
¢      6           \ëÂ          
«         
R        ùdefault state_uhs              O   P        
n   O         
²         
¿        
x   Q        
„   R      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          *    %             æ                 “       ˆ               V   !       "      "   I        Gsource hclk source_cg           e   !            u   !   ¿      	  £disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            *    '€                “       ª               V   "           ð   "           6   ?   @      $  Blvts-calib-data-1 lvts-calib-data-2         S              »      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           *    )             )>              	  Dmac ippc            “                     	¬   S           e   !   .   !   /        u   !   –   !   –      $  V   1      !   ï             1         $  Gsys_ck ref_ck mcu_ck dma_ck xhci_ck         	±   H      h         j        £okay            	Þ           	Ð   I        	ì   J        
Í         usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           *    *       -ÿ    *>              	  Dmac ippc            ¿            *        ?                      +           “                     e   !   0        u   !   –        V   1      !   ñ   1           Gsys_ck ref_ck mcu_ck            	¬   T            j        	±   H      i        £okay            	Èhost            	Ð   I   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          *                       Dmac         “                     e   !   1        u   !   –        V   1           Gsys_ck          £okay            	ì   J         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           *    +       -ÿ    +>              	  Dmac ippc            ¿            +        ?                      +           “                     e   !   2        u   !   –        V   1      !   ó   1   	        Gsys_ck ref_ck mcu_ck            	¬   U            j        	±   H      j        £okay            	Èhost            	Ð   I   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          *                       Dmac         “                     e   !   3        u   !   –        V   1   	        Gsys_ck          £okay             
â        	ì   J         pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +           *    /        @       	  Dpcie-mac            “                     
ó       ÿ      8  ¿�                           ‚                       à          
ý       V                        0  V   "   V   "   #   "   &   "   +   "   K   1         /  Gpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          e   !   G        u   !           	¬   W      	  pcie-phy            ¾   6            Ñ                                 `  3                  X                      X                     X                     X         	  £disabled       interrupt-controller             ù                     Ñ              X         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +           *    /€       @       	  Dpcie-mac            “                     
ó       ÿ      8  ¿�       $       $           ‚       $       $       à          
ý       V                        (  V   "   W      "   X      "   Q   1         /  Gpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          e   !   H        u   !           	¬   Y         	  pcie-phy            ¾   6           Ñ                                 `  3                  Z                      Z                     Z                     Z           £okay            ùdefault            [   interrupt-controller             ù                     Ñ              Z         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         *    2À                “      9               V   !   o   1      1           Gspi sf axi                       +            £okay            ùdefault            \   flash@0           jedec,spi-nor           *            Xu         A           R            efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            *    Á                              +      usb3-tx-imp@184,1           *  „           c                  s      usb3-rx-imp@184,2           *  „           c                 r      usb3-intr@185           *  …           c                 q      usb3-tx-imp@186,1           *  †           c                  p      usb3-rx-imp@186,2           *  †           c                 o      usb3-intr@187           *  ‡           c                 n      usb2-intr-p0@188,1          *  ˆ           c             usb2-intr-p1@188,2          *  ˆ           c            usb2-intr-p2@189,1          *  ‰           c            usb2-intr-p3@189,2          *  ‰           c            pciephy-rx-ln1@190,1            *  �           c                  z      pciephy-tx-ln1-nmos@190,2           *  �           c                 y      pciephy-tx-ln1-pmos@191,1           *  ‘           c                  x      pciephy-rx-ln0@191,2            *  ‘           c                 w      pciephy-tx-ln0-nmos@192,1           *  ’           c                  v      pciephy-tx-ln0-pmos@192,2           *  ’           c                 u      pciephy-glb-intr@193            *  “           c                  t      dp-data@1ac         *  ¬              ²      lvts1-calib@1bc         *  ¼              ?      lvts2-calib@1d0         *  Ð   8           @      svs-calib@580           *  €   d           A      socinfo-data1@7a0           *               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ¿        Ä             £okay       usb-phy@0           *               V   !   ò        Gref         h              T         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ¿        Å             £okay       usb-phy@0           *               V   !   ô        Gref         h              U         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         *    È                 V           rmipi_tx0_pll            I            h          	  £disabled                      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         *    É                 V           rmipi_tx1_pll            I            h          	  £disabled               ¡      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *    Ð             "€       €        “       š               ]           V   ]       "   ;      	  Gmain dma                         +            £okay            P €        ùdefault            ^      i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *    Ð            "        €        “       ›               ]           V   ]      "   ;      	  Gmain dma                         +          	  £disabled          i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *    Ð             "€       €        “       œ               ]           V   ]      "   ;      	  Gmain dma                         +            £okay            P €        ùdefault            _   pmic@34         Ñ             mediatek,mt6360         *   4         ù        Œ      ‚           tIRQB            ùdefault            `         j         clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          *    Ð0                I              ]      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *    à             " €       €        “       �               ]           V   a       "   ;      	  Gmain dma                         +            £okay            P €        ùdefault            b      i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *    à            "        €        “       “               ]           V   a      "   ;      	  Gmain dma                         +            £okay            P €        s  0Ô        ùdefault            c   trackpad@15           elan,ekth3000           *           Œ                 ùdefault            d        �   e         j         i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *    à             "€       €        “       –               ]           V   a      "   ;      	  Gmain dma                         +            £okay            P €        ùdefault            f   codec@1a            *           Œ      Y           ˜           ©           ¸   g        Ä   h        Ò   i          realtek,rt5682i         Þ                       i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *    à0            "€       €        “       ˜               ]           V   a      "   ;      	  Gmain dma                         +            £okay            P €        ùdefault            j   tpm@50            google,cr50         *   P        Œ      X           ùdefault            k         i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          *    à@            "        €        “       ™               ]           V   a      "   ;      	  Gmain dma                         +            £okay            P €        ùdefault            l   touchscreen@10            hid-over-i2c            *           ó           Œ      \           ùdefault            m           
           e        £okay             clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          *    àP                I              a      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ¿        ã             ¾   6           £okay       usb-phy@0           *               V   !   ð           Gref da_ref          h              S      usb-phy@700         *              V          !   ð        Gref da_ref          6   n   o   p        Bintr rx_imp tx_imp          h              Y         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           ¿        ä             £okay       usb-phy@0           *               V   !   î           Gref da_ref          h              F      usb-phy@700         *              V          !   î        Gref da_ref          6   q   r   s        Bintr rx_imp tx_imp          h              G         phy@11e80000              mediatek,mt8195-pcie-phy            *    è                 Dsif         6   t   u   v   w   x   y   z      G  Bglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          ¾   6           h          	  £disabled               W      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           *    ú        À         V            
  Gunipro mp           h          	  £disabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           *             @         V   {          0  “      �             Œ             ‹               tjob mmu gpu         $   |      (  ¾   6   
   6      6      6      6           8core0 core1 core2 core3 core4           £okay            K         clock-controller@13fbf000             mediatek,mt8195-mfgcfg          *    ûð                I              {      syscon@14000000           mediatek,mt8195-vppsys0 syscon          *                      I           W   }                      $      dma-controller@14001000           mediatek,mt8195-mdp3-rdma           *                     W   }                  o              ƒ   ~        ¾   6           �      €        V   $         <  ×   }         }         }         }         }              —         display@14002000              mediatek,mt8195-mdp3-fg         *                      W   }                   V   $          display@14003000              mediatek,mt8195-mdp3-stitch         *     0                W   }      0            V   $         display@14004000              mediatek,mt8195-mdp3-hdr            *     @                W   }      @            V   $   "      display@14005000              mediatek,mt8195-mdp3-aal            *     P                “      F               W   }      P            V   $   
        ¾   6         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           *     `                W   }      `            o    %        V   $         display@14007000              mediatek,mt8195-mdp3-tdshp          *     p                W   }      p            V   $   #      display@14008000              mediatek,mt8195-mdp3-color          *     €                “      I               W   }      €            V   $   $        ¾   6         display@14009000              mediatek,mt8195-mdp3-ovl            *     �                “      J               W   }      �            V   $   %        ¾   6           �      ‚      display@1400a000              mediatek,mt8195-mdp3-padding            *                      W   }                   V   $           ¾   6         display@1400b000              mediatek,mt8195-mdp3-tcc            *     °                W   }      °            V   $         dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         *     À                W   }      À            o    +        V   $           �      ƒ        ¾   6           —         mutex@1400f000            mediatek,mt8195-vpp-mutex           *     ð                “      P               W   }      ð            V   $           ¾   6         smi@14010000              mediatek,mt8195-smi-sub-common          *                     V   $      $      $           Gapb smi gals0           ¢   €        ¾   6              �      smi@14011000              mediatek,mt8195-smi-sub-common          *                    V   $      $      $           Gapb smi gals0           ¢   €        ¾   6              ž      smi@14012000              mediatek,mt8195-smi-common-vpp          *                      V   $      $      $      $           Gapb smi gals0 gals1         ¾   6              €      larb@14013000             mediatek,mt8195-smi-larb            *    0                ¯           ¢   �        V   $      $           Gapb smi         ¾   6              „      iommu@14018000            mediatek,mt8195-iommu-vpp           *    €              8  À   ‚   ƒ   „   …   †   ‡   ˆ   ‰   Š   ‹   Œ   �   Ž   �        “      R               V   $           Gbclk            u           ¾   6                    clock-controller@14e00000             mediatek,mt8195-wpesys          *    à                 I              '      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         *    à                 I         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         *    à0                I         larb@14e04000             mediatek,mt8195-smi-larb            *    à@                ¯           ¢   �        V   '      '           Gapb smi         ¾   6              ¦      larb@14e05000             mediatek,mt8195-smi-larb            *    àP                ¯           ¢   €        V   '      '      $           Gapb smi gals            ¾   6              †      syscon@14f00000           mediatek,mt8195-vppsys1 syscon          *    ð                 I           W   }   	                  &      mutex@14f01000            mediatek,mt8195-vpp-mutex           *    ð                “      {               W   }   	              V   &   '        ¾   6         larb@14f02000             mediatek,mt8195-smi-larb            *    ð                 ¯           ¢   �        V   &      &      $           Gapb smi gals            ¾   6              ¥      larb@14f03000             mediatek,mt8195-smi-larb            *    ð0                ¯           ¢   �        V   &      &      $           Gapb smi gals            ¾   6              …      display@14f06000              mediatek,mt8195-mdp3-split          *    ð`                W   }   	  `            V   &      &   +   &   ,        ¾   6         display@14f07000              mediatek,mt8195-mdp3-tcc            *    ðp                W   }   	  p            V   &         dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           *    ð€                W   }   	  €            o  „  ¨        V   &           �   ‘            ¾   6           —         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           *    ð�                W   }   	  �            o  …  ©        V   &   
        �   ‘   ¤        ¾   6           —         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           *    ð                 W   }   	               o  †  ª        V   &           �      À        ¾   6           —         display@14f0b000              mediatek,mt8195-mdp3-fg         *    ð°                W   }   	  °            V   &   	      display@14f0c000              mediatek,mt8195-mdp3-fg         *    ðÀ                W   }   	  À            V   &         display@14f0d000              mediatek,mt8195-mdp3-fg         *    ðÐ                W   }   	  Ð            V   &         display@14f0e000              mediatek,mt8195-mdp3-hdr            *    ðà                W   }   	  à            V   &         display@14f0f000              mediatek,mt8195-mdp3-hdr            *    ðð                W   }   	  ð            V   &         display@14f10000              mediatek,mt8195-mdp3-hdr            *    ñ                 W   }   
               V   &          display@14f11000              mediatek,mt8195-mdp3-aal            *    ñ                “      i               W   }   
              V   &           ¾   6         display@14f12000              mediatek,mt8195-mdp3-aal            *    ñ                 “      j               W   }   
               V   &           ¾   6         display@14f13000              mediatek,mt8195-mdp3-aal            *    ñ0                “      k               W   }   
  0            V   &   !        ¾   6         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           *    ñ@                W   }   
  @            o  �  ¯        V   &         display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           *    ñP                W   }   
  P            o  ‘  °        V   &   $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           *    ñ`                W   }   
  `            o  ’  ±        V   &   %      display@14f17000              mediatek,mt8195-mdp3-tdshp          *    ñp                W   }   
  p            V   &         display@14f18000              mediatek,mt8195-mdp3-tdshp          *    ñ€                W   }   
  €            V   &   (      display@14f19000              mediatek,mt8195-mdp3-tdshp          *    ñ�                W   }   
  �            V   &   )      display@14f1a000              mediatek,mt8195-mdp3-merge          *    ñ                 W   }   
               V   &           ¾   6         display@14f1b000              mediatek,mt8195-mdp3-merge          *    ñ°                W   }   
  °            V   &           ¾   6         display@14f1c000              mediatek,mt8195-mdp3-color          *    ñÀ                “      t               W   }   
  À            V   &           ¾   6         display@14f1d000              mediatek,mt8195-mdp3-color          *    ñÐ                W   }   
  Ð            “      u               V   &           ¾   6         display@14f1e000              mediatek,mt8195-mdp3-color          *    ñà                “      v               W   }   
  à            V   &           ¾   6         display@14f1f000              mediatek,mt8195-mdp3-ovl            *    ñð                “      w               W   }   
  ð            V   &            ¾   6           �   ‘   ¢      display@14f20000              mediatek,mt8195-mdp3-padding            *    ò                 W   }                  V   &           ¾   6         display@14f21000              mediatek,mt8195-mdp3-padding            *    ò                W   }                 V   &           ¾   6         display@14f22000              mediatek,mt8195-mdp3-padding            *    ò                 W   }                  V   &           ¾   6         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         *    ò0                W   }     0            o  Ÿ  «        V   &           �   ‘   £        ¾   6           —         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         *    ò@                W   }     @            o     ¬        V   &           �   ‘   ¦        ¾   6           —         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         *    òP                W   }     P            o  ¡  ­        V   &           �      Â        ¾   6           —         clock-controller@15000000             mediatek,mt8195-imgsys          *                      I              .      larb@15001000             mediatek,mt8195-smi-larb            *                     ¯   	        ¢   ’        V   .       .       .   
        Gapb smi gals            ¾   6              §      smi@15002000              mediatek,mt8195-smi-sub-common          *                      V   .      .      $           Gapb smi gals0           ¢   €        ¾   6              •      smi@15003000              mediatek,mt8195-smi-sub-common          *     0                V   .       .       .   
        Gapb smi gals0           ¢   �        ¾   6              ’      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         *                     I              “      larb@15120000             mediatek,mt8195-smi-larb            *                     ¯   
        ¢   ’        V   .      “            Gapb smi         ¾   6              ¨      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          *                     I         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         *    "                 I              ”      larb@15230000             mediatek,mt8195-smi-larb            *    #                 ¯           ¢   ’        V   .      ”            Gapb smi         ¾   6              ©      clock-controller@15330000             mediatek,mt8195-ipesys          *    3                 I              /      larb@15340000             mediatek,mt8195-smi-larb            *    4                 ¯           ¢   •        V   /      /           Gapb smi         ¾   6              ‡      clock-controller@16000000             mediatek,mt8195-camsys          *                      I              0      larb@16001000             mediatek,mt8195-smi-larb            *                     ¯           ¢   –        V   0       0       0           Gapb smi gals            ¾   6              ª      larb@16002000             mediatek,mt8195-smi-larb            *                      ¯           ¢   —        V   0      0           Gapb smi         ¾   6              ˆ      smi@16004000              mediatek,mt8195-smi-sub-common          *     @                V   0       0       0           Gapb smi gals0           ¢   �        ¾   6              –      smi@16005000              mediatek,mt8195-smi-sub-common          *     P                V   0      0      $           Gapb smi gals0           ¢   €        ¾   6              —      larb@16012000             mediatek,mt8195-smi-larb            *                     ¯           ¢   —        V   ˜       ˜            Gapb smi         ¾   6               ‰      larb@16013000             mediatek,mt8195-smi-larb            *    0                ¯           ¢   –        V   ™       ™            Gapb smi         ¾   6               «      larb@16014000             mediatek,mt8195-smi-larb            *    @                ¯           ¢   —        V   š       š            Gapb smi         ¾   6   !           �      larb@16015000             mediatek,mt8195-smi-larb            *    P                ¯           ¢   –        V   ›       ›            Gapb smi         ¾   6   !           °      clock-controller@1604f000             mediatek,mt8195-camsys_rawa         *    ð                I              ˜      clock-controller@1606f000             mediatek,mt8195-camsys_yuva         *    ð                I              ™      clock-controller@1608f000             mediatek,mt8195-camsys_rawb         *    ð                I              š      clock-controller@160af000             mediatek,mt8195-camsys_yuvb         *    
ð                I              ›      clock-controller@16140000             mediatek,mt8195-camsys_mraw         *                     I              œ      larb@16141000             mediatek,mt8195-smi-larb            *                    ¯           ¢   –        V   0       œ       0           Gapb smi gals            ¾   6   "           ¯      larb@16142000             mediatek,mt8195-smi-larb            *                     ¯           ¢   —        V   œ       œ            Gapb smi         ¾   6   "           Ž      clock-controller@17200000             mediatek,mt8195-ccusys          *                      I              �      larb@17201000             mediatek,mt8195-smi-larb            *                     ¯           ¢   —        V   �       �            Gapb smi         ¾   6              Š      video-codec@18000000              mediatek,mt8195-vcodec-dec          ƒ   ~        �   ‘                        +            *                   @                ¿                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         *                       �     à     á         V   !   A   (      (      !   �        Gsel vdec lat top            e   !   A        u   !   �        ¾   6         video-codec@10000             mediatek,mtk-vcodec-lat         *                      “      Ä             0  �   ‘      ‘     ‘     ‘     ‘     ‘           V   !   A   (      (      !   �        Gsel vdec lat top            e   !   A        u   !   �        ¾   6         video-codec@25000             mediatek,mtk-vcodec-core            *     P                “      Ã             P  �   ‘      ‘  ¡   ‘  ¢   ‘  £   ‘  ¤   ‘  ¥   ‘  ¦   ‘  §   ‘  ¨   ‘  ©         V   !   A   )      )      !   �        Gsel vdec lat top            e   !   A        u   !   �        ¾   6            larb@1800d000             mediatek,mt8195-smi-larb            *     Ð                ¯           ¢   �        V   (       (            Gapb smi         ¾   6              ®      larb@1800e000             mediatek,mt8195-smi-larb            *     à                ¯           ¢   ž        V   $      (            Gapb smi         ¾   6              �      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         *     ð                I              (      larb@1802e000             mediatek,mt8195-smi-larb            *    à                ¯           ¢   �        V   )       )            Gapb smi         ¾   6              ­      clock-controller@1802f000             mediatek,mt8195-vdecsys         *    ð                I              )      larb@1803e000             mediatek,mt8195-smi-larb            *    à                ¯           ¢   ž        V   $      *            Gapb smi         ¾   6              Œ      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           *    ð                I              *      clock-controller@190f3000             mediatek,mt8195-apusys_pll          *    0                I         clock-controller@1a000000             mediatek,mt8195-vencsys         *                      I              +      larb@1a010000             mediatek,mt8195-smi-larb            *                     ¯           ¢   �        V   +      +           Gapb smi         ¾   6              ¬      video-codec@1a020000              mediatek,mt8195-vcodec-enc          *                   H  �   ‘  `   ‘  a   ‘  b   ‘  c   ‘  d   ‘  v   ‘  w   ‘  x   ‘  y        “      U               ƒ   ~        V   +         	  Gvenc_sel            e   !   @        u   !   �        ¾   6                        +         jpgdec-master             mediatek,mt8195-jpgdec          ¾   6         0  �   ‘  m   ‘  n   ‘  r   ‘  s   ‘  t   ‘  u                     +            ¿   jpgdec@1a040000           mediatek,mt8195-jpgdec-hw           *                   0  �   ‘  m   ‘  n   ‘  r   ‘  s   ‘  t   ‘  u        “      W               V   +           Gjpgdec          ¾   6         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw           *                   0  �   ‘  m   ‘  n   ‘  r   ‘  s   ‘  t   ‘  u        “      X               V   +           Gjpgdec          ¾   6         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw           *                   0  �     �     Ž     ’     “     ”     •        “      \               V   ,           Gjpgdec          ¾   6            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           *                      I              ,      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            *                     ×   Ÿ               I           W   Ÿ                     %      jpgenc-master             mediatek,mt8195-jpgenc          ¾   6            �     ‡     ˆ     ‰     Œ                     +            ¿   jpgenc@1a030000           mediatek,mt8195-jpgenc-hw           *                      �   ‘  g   ‘  h   ‘  i   ‘  l        “      V               V   +           Gjpgenc          ¾   6         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw           *                      �     ‡     ˆ     ‰     Œ        “      [               V   ,           Gjpgenc          ¾   6            larb@1b010000             mediatek,mt8195-smi-larb            *                     ¯           ¢   €        V   ,      ,      $            Gapb smi gals            ¾   6              ‹      ovl@1c000000              mediatek,mt8195-disp-ovl            *                      “      |               ¾   6           V   %            �   ‘           W   Ÿ                rdma@1c002000             mediatek,mt8195-disp-rdma           *                      “      ~               ¾   6           V   %           �   ‘            W   Ÿ                color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           *     0                “                     ¾   6           V   %           W   Ÿ     0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           *     @                “      €               ¾   6           V   %           W   Ÿ     @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           *     P                “      �               ¾   6           V   %           W   Ÿ     P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           *     `                “      ‚               ¾   6           V   %           W   Ÿ     `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         *     p                “      ƒ               ¾   6           V   %   	        W   Ÿ     p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         *     €                “      „               ¾   6           V   %      %   *            Gengine digital hs           	¬            dphy          	  £disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            *     �                “      …               ¾   6           V   %           W   Ÿ     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         *                     “      Ž               ¾   6           V   %      %   +   ¡        Gengine digital hs           	¬   ¡        dphy          	  £disabled          merge@1c014000            mediatek,mt8195-disp-merge          *    @                “      �               ¾   6           V   %           W   Ÿ     @          dp-intf@1c015000              mediatek,mt8195-dp-intf         *    P                “      ‘               V   %   ,   %                  Gpixel engine pll            £okay       port       endpoint            Ï   ¢           ´            mutex@1c016000            mediatek,mt8195-disp-mutex          *    `                “      ’               ¾   6           V   %           W   Ÿ     `            o  U      larb@1c018000             mediatek,mt8195-smi-larb            *    €                ¯            ¢   �        V   %   (   %   (   $           Gapb smi gals            ¾   6              £      larb@1c019000             mediatek,mt8195-smi-larb            *    �                ¯           ¢   €        V   %   (   $       $           Gapb smi gals            ¾   6              ‚      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          *                     ×   Ÿ              W   Ÿ                  I           7              -      smi@1c01b000              mediatek,mt8195-smi-common-vdo          *    °                 V   %   %   %   &   %   )   %   $        Gapb smi gals0 gals1         ¾   6              �      iommu@1c01f000            mediatek,mt8195-iommu-vdo           *    ð              8  À   £   ¤   ¥   ¦   §   ¨   ©   ª   «   ¬   ­   ®   ¯   °        “      �               u           V   %   '        Gbclk            ¾   6              ‘      mutex@1c101000            mediatek,mt8195-disp-mutex          *                    “      î               ¾   6           V   -           W   Ÿ                 o  À      larb@1c102000             mediatek,mt8195-smi-larb            *                     ¯           ¢   �        V   -       -       -           Gapb smi gals            ¾   6              ¤      larb@1c103000             mediatek,mt8195-smi-larb            *    0                ¯           ¢   €        V   -      -      $            Gapb smi gals            ¾   6              ƒ      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           *    @                “      ï               V   -           ¾   6           �   ‘   @        W   Ÿ     @            —         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           *    P                “      ð               V   -           ¾   6           �      `        W   Ÿ     P            —         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           *    `                “      ñ               V   -           ¾   6           �   ‘   A        W   Ÿ     `            —         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           *    p                “      ò               V   -           ¾   6           �      a        W   Ÿ     p            —         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           *    €                “      ó               V   -           ¾   6           �   ‘   B        W   Ÿ     €            —         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           *    �                “      ô               V   -           ¾   6           �      b        W   Ÿ     �            —         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           *                     “      õ               V   -           ¾   6           �   ‘   C        W   Ÿ                  —         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           *    °                “      ö               V   -           ¾   6           �      c        W   Ÿ     °            —         vpp-merge@1c10c000            mediatek,mt8195-disp-merge          *    À                “      ÷               V   -   	   -           Gmerge merge_async           ¾   6           W   Ÿ     À             ß        ð   -         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          *    Ð                “      ø               V   -   
   -           Gmerge merge_async           ¾   6           W   Ÿ     Ð             ß        ð   -         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          *    à                “      ù               V   -      -           Gmerge merge_async           ¾   6           W   Ÿ     à             ß        ð   -         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          *    ð                “      ú               V   -      -           Gmerge merge_async           ¾   6           W   Ÿ     ð             ß        ð   -         vpp-merge@1c110000            mediatek,mt8195-disp-merge          *                     “      û               V   -      -           Gmerge merge_async           ¾   6           W   Ÿ                   ó        ð   -         dp-intf@1c113000              mediatek,mt8195-dp-intf         *    0                “                     ¾   6           V   -   /   -                  Gpixel engine pll            £okay       port       endpoint            Ï   ±           º            hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  *    @            P            p            �                         °            À              4  Dmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  W   Ÿ     @       Ÿ     P       Ÿ     p       Ÿ     �       Ÿ             Ÿ     °       Ÿ     À          h  V   -   %   -       -   #   -   !   -   $   -   "   -   1   -   &   -   '   -   (   -   )   -   *   !         ƒ  Gmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          ¾   6           �      d      e        “                   (  ð   -   3   -   4   -   5   -   6   -   7      E  ÷vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx          *    P        €         6   ²        Bdp_calibration_data         ¾   6           “      ¤               
  ¤        £okay            ùdefault            ³   ports                        +       port@0          *       endpoint            Ï   ´           ¢         port@1          *      endpoint                                 Ï   µ           ¸            aux-bus    panel         
    edp-panel           &   ¶        3   ·   port       endpoint            Ï   ¸           µ                  dp-tx@1c600000            mediatek,mt8195-dp-tx           *    `        €         6   ²        Bdp_calibration_data         ¾   6           “      Ê               
  ¤        £okay            ˜            ùdefault            ¹              ports                        +       port@0          *       endpoint            Ï   º           ±         port@1          *      endpoint                                           thermal-zones      cpu0-thermal            =  è        K   ú        a   »      trips      trip-alert          q L        }  Ð        %passive            ¼      trip-crit           q †         }  Ð      	  %critical             cooling-maps       map0            ˆ   ¼      0  �   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            =  è        K   ú        a   »      trips      trip-alert          q L        }  Ð        %passive            ½      trip-crit           q †         }  Ð      	  %critical             cooling-maps       map0            ˆ   ½      0  �   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            =  è        K   ú        a   »      trips      trip-alert          q L        }  Ð        %passive            ¾      trip-crit           q †         }  Ð      	  %critical             cooling-maps       map0            ˆ   ¾      0  �   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            =  è        K   ú        a   »      trips      trip-alert          q L        }  Ð        %passive            ¿      trip-crit           q †         }  Ð      	  %critical             cooling-maps       map0            ˆ   ¿      0  �   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            =  è        K   ú        a   »       trips      trip-alert          q L        }  Ð        %passive            À      trip-crit           q †         }  Ð      	  %critical             cooling-maps       map0            ˆ   À      0  �   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            =  è        K   ú        a   »      trips      trip-alert          q L        }  Ð        %passive            Á      trip-crit           q †         }  Ð      	  %critical             cooling-maps       map0            ˆ   Á      0  �   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            =  è        K   ú        a   »      trips      trip-alert          q L        }  Ð        %passive            Â      trip-crit           q †         }  Ð      	  %critical             cooling-maps       map0            ˆ   Â      0  �   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            =  è        K   ú        a   »      trips      trip-alert          q L        }  Ð        %passive            Ã      trip-crit           q †         }  Ð      	  %critical             cooling-maps       map0            ˆ   Ã      0  �   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            =  è        K   ú        a   Ä      trips      trip-alert          q L        }  Ð        %passive       trip-crit           q †         }  Ð      	  %critical                vpu1-thermal            =  è        K   ú        a   Ä   	   trips      trip-alert          q L        }  Ð        %passive       trip-crit           q †         }  Ð      	  %critical                gpu-thermal         =  è        K   ú        a   Ä   
   trips      trip-alert          q L        }  Ð        %passive       trip-crit           q †         }  Ð      	  %critical                gpu1-thermal            =  è        K   ú        a   Ä      trips      trip-alert          q L        }  Ð        %passive       trip-crit           q †         }  Ð      	  %critical                vdec-thermal            =  è        K   ú        a   Ä      trips      trip-alert          q L        }  Ð        %passive       trip-crit           q †         }  Ð      	  %critical                img-thermal         =  è        K   ú        a   Ä      trips      trip-alert          q L        }  Ð        %passive       trip-crit           q †         }  Ð      	  %critical                infra-thermal           =  è        K   ú        a   Ä      trips      trip-alert          q L        }  Ð        %passive       trip-crit           q †         }  Ð      	  %critical                cam0-thermal            =  è        K   ú        a   Ä      trips      trip-alert          q L        }  Ð        %passive       trip-crit           q †         }  Ð      	  %critical                cam1-thermal            =  è        K   ú        a   Ä      trips      trip-alert          q L        }  Ð        %passive       trip-crit           q †         }  Ð      	  %critical                soc-area-thermal            =  è        K   ú        a   Å   trips      trip-crit           q H         }  è      	  %critical                pmic-area-thermal           =  è        K            a   Æ   trips      trip-crit           q H         }  è      	  %critical                   backlight-lcd0            pwm-backlight           œ      ÿ        ®  @        Ç      R            Ô  ÿ        ë   Ç     ¡         &   È           ·      chosen          ðserial0:115200n8          memory@40000000         memory          *    @       €         regulator-pp3300-disp-x           regulator-fixed         Ùpp3300_disp_x           è 2Z           2Z           	Ä         ü              7            ùdefault            É           h           ¶      regulator-pp3300-ldo-z5           regulator-fixed         Ùpp3300_ldo_z5            4                 è 2Z           2Z            È           i      regulator-pp3300-s3           regulator-fixed       
  Ùpp3300_s3            4                 è 2Z           2Z            h           e      regulator-pp3300-z2           regulator-fixed       
  Ùpp3300_z2            4                 è 2Z           2Z            È           h      regulator-pp4200-z2           regulator-fixed       
  Ùpp4200_z2            4                 è @@          @@           È      regulator-pp5000-s5           regulator-fixed       
  Ùpp5000_s5            4                 è LK@          LK@           È      regulator-ppvar-sys           regulator-fixed       
  Ùppvar_sys            4                    È      thermal-sensor-t1             generic-adc-thermal         S            1   Ê            =sensor-channel        à  NÿÿØð  ÿÿìx  Í      ~  ˆ  %  '  Ã  :˜  [  N   ï  a¨  „  u0    ˆ¸  ¹  œ@  ]  ¯È    ÃP  Á  ÖØ  €  ê`  G  ýè   p   í $ø   Ê 8€   ¬ L   “ _�   } s   k †    \ š(   O ­°   D Á8   ; ÔÀ   3 èH   ,           Å      thermal-sensor-t2             generic-adc-thermal         S            1   Ê           =sensor-channel        à  NÿÿØð  ÿÿìx  Í      ~  ˆ  %  '  Ã  :˜  [  N   ï  a¨  „  u0    ˆ¸  ¹  œ@  ]  ¯È    ÃP  Á  ÖØ  €  ê`  G  ýè   p   í $ø   Ê 8€   ¬ L   “ _�   } s   k †    \ š(   O ­°   D Á8   ; ÔÀ   3 èH   ,           Æ      regulator-5v0-usb-vbus            regulator-fixed       	  Ùusb-vbus            è LK@          LK@         ü         4           J      reserved-memory                      +            ¿   memory@50000000           shared-dma-pool         *    P       �           g           3      memory@60000000           shared-dma-pool         *    `        Ø           g           :      memory@60d80000           shared-dma-pool         *    `Ø                  g           <      memory@60e80000           shared-dma-pool         *    `è       (           g           9         rt1019p           realtek,rt1019p         nrt1019p         ˜            ùdefault            Ë        t      d                        	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c0 i2c1 i2c2 i2c3 i2c4 i2c5 i2c7 mmc0 mmc1 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform mediatek,adsp mediatek,dai-link pinctrl-names pinctrl-0 audio-routing link-name mediatek,clk-provider sound-dai #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller mediatek,broken-save-restore-fw affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit gpio-line-names pinmux input-enable bias-pull-up bias-disable drive-strength-microamp drive-strength bias-pull-down output-high output-low #power-domain-cells domain-supply clock-names mediatek,infracfg assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells mediatek,dmic-mode mediatek,mic-type-0 regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells firmware-name memory-region mediatek,rpmsg-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names mediatek,etdm-in2-cowork-source mediatek,etdm-out2-cowork-source mediatek,pad-select spi-max-frequency wakeup-source google,remote-bus sbs,i2c-retry-count sbs,poll-retry-count power-role data-role try-power-role keypad,num-rows keypad,num-columns google,needs-ghost-filter linux,keymap function-row-physmap nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys mediatek,syscon-wakeup dr_mode vusb33-supply rx-fifo-depth vbus-supply bus-width cap-mmc-highspeed cap-mmc-hw-reset hs400-ds-delay mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable pinctrl-1 vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 mediatek,u3p-dis-msk usb2-lpm-disable bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-rx-bus-width spi-tx-bus-width bits #phy-cells i2c-scl-internal-delay-ns vcc-supply #sound-dai-cells realtek,jd-src AVDD-supply MICVDD-supply VBAT-supply realtek,btndet-delay hid-descr-addr post-power-on-delay-ms vdd-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs remote-endpoint mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz data-lanes power-supply backlight polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device brightness-levels default-brightness-level enable-gpios num-interpolated-steps pwms stdout-path enable-active-high gpio vin-supply regulator-boot-on io-channels io-channel-names temperature-lookup-table no-map label sdb-gpios 