Ðþí Cû   8 9x   (            
ƒ 9@                             %    mediatek,mt8195-demo mediatek,mt8195                                     +            7MediaTek MT8195 demo board     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          ƒ/soc/vpp-merge@1c10f000          Š/soc/vpp-merge@1c110000          ‘/soc/dma-controller@1c104000             œ/soc/dma-controller@1c105000             §/soc/dma-controller@1c106000             ²/soc/dma-controller@1c107000             ½/soc/dma-controller@1c108000             È/soc/dma-controller@1c109000             Ó/soc/dma-controller@1c10a000             Þ/soc/dma-controller@1c10b000             é/soc/serial@11001100          cpus                         +       cpu@0            ñcpu           arm,cortex-a55           ý            psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î   	      cpu@100          ñcpu           arm,cortex-a55           ý           psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î   
      cpu@200          ñcpu           arm,cortex-a55           ý           psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î         cpu@300          ñcpu           arm,cortex-a55           ý           psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î         cpu@400          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu@500          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu@600          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu@700          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu-map    cluster0       core0           Ö   	      core1           Ö   
      core2           Ö         core3           Ö         core4           Ö         core5           Ö         core6           Ö         core7           Ö               idle-states         Úpsci       cpu-retention-l           arm,idle-state          ç           þ           2            _        0  D        Î         cpu-retention-b           arm,idle-state          ç           þ           -            Œ        0  ä        Î         cpu-off-l             arm,idle-state          ç          þ           7            ›        0  H        Î         cpu-off-b             arm,idle-state          ç          þ           2            È        0  è        Î            l2-cache0             cache           A           X           e   @        w           ®            M        Î         l2-cache1             cache           A           X           e   @        w           ®            M        Î         l3-cache              cache           A           X            e   @        w            M        Î            dsu-pmu           arm,dsu-pmu         [                       f   	   
                          kfail          dmic-codec            dmic-codec          r              2      mt8195-sound            �         	  kdisabled          fixed-factor-clock-13m            fixed-factor-clock          ¡            ®           µ           ¿           Êclk13m          Î   (      oscillator-26m            fixed-clock         ¡            #Œº€        Êclk26m          Î         oscillator-32k            fixed-clock         ¡            #  €         Êclk32k        performance-controller@11bc10             mediatek,cpufreq-hw           ý     ¼            ½0               Ý           Î         opp-table-gpu             operating-points-v2          ÷        Î   `   opp-390000000               >í€        	 	‰h      opp-410000000               p€        	 	¡Ò      opp-431000000               °‰À        	 	¡Ò      opp-473000000               1h@        	 	º<      opp-515000000               ²FÀ        	 	º<      opp-556000000               !#ã         	 	Ò¦      opp-598000000               #¤Á€        	 	ë      opp-640000000               &%          	 	ë      opp-670000000               'ïc€        	 
ä      opp-700000000               )¹'         	 
L¸      opp-730000000               +‚ê€        	 
}Œ      opp-760000000               -L®         	 
®`      opp-790000000               /q€        	 
ß4      opp-820000000               0à5         	       opp-850000000               2©ø€        	 @Ü      opp-880000000               4s¼         	 q°         pmu-a55           arm,cortex-a55-pmu                      [                  pmu-a78           arm,cortex-a78-pmu                      [                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  [                                             
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3          )           :                        Q          ý                                    [      	               Î      ppi-partitions     interrupt-partition-0           f   	   
              Î         interrupt-partition-1           f                    Î               syscon@10000000            mediatek,mt8195-topckgen syscon          ý                      ¡           Î         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon           ý                     ¡           o           Î         syscon@10003000           mediatek,mt8195-pericfg syscon           ý     0                ¡           Î   ;      pinctrl@10005000              mediatek,mt8195-pinctrl       €   ý     P            Ñ             Ó             Ô             â             ë             ô              °              B  |iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            †        –           ¢              �         Q        [       ë               )           Î      eth-default-pins            Î   7   pins-txd            ®  M  N  O  P        µ         pins-cc         ®  U  X  W  V        µ         pins-rxd            ®  Q  R  S  T      pins-mdio           ®  Y  Z         Ä      pins-power          ®  [   \          Ñ         eth-sleep-pins          Î   8   pins-txd            ®  M   N   O   P       pins-cc         ®  U   X   W   V       pins-rxd            ®  Q   R   S   T       pins-mdio           ®  Y   Z          Ý         ë         gpio-keys-pins          Î   Ÿ   pins            ®  j          Ä         i2c6-pins           Î   O   pins            ®             ø         mmc0-default-pins           Î   >   pins-clk            ®  z        µ              f      pins-cmd-dat          $  ®  ~  }  |  {  w  v  u  t  y         Ä        µ           ø   e      pins-rst            ®  x        µ           ø   e         mmc0-uhs-pins           Î   ?   pins-clk            ®  z        µ              f      pins-cmd-dat          $  ®  ~  }  |  {  w  v  u  t  y         Ä        µ           ø   e      pins-ds         ®          µ              f      pins-rst            ®  x        µ           ø   e         mmc1-default-pins           Î   B   pins-clk            ®  o        µ              f      pins-cmd-dat            ®  n  p  q  r  s         Ä        µ           ø   e      pins-insert         ®  �          ø         mmc1-uhs-pins           Î   C   pins-clk            ®  o        µ              f      pins-cmd-dat            ®  n  p  q  r  s         Ä        µ           ø   e         uart0-pins          Î   .   pins            ®  b  c         uart1-pins          Î   /   pins            ®  f  g            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd             ý     `           power-controller          !    mediatek,mt8195-power-controller                         +                       Î   *   power-domain@8           ý                        +                  power-domain@9           ý   	        ®                    (mfg alt         4                        +                  power-domain@10          ý   
                  power-domain@11          ý                     power-domain@12          ý                     power-domain@13          ý                     power-domain@14          ý                           power-domain@15          ý         Ø  ®                        	      @      A      K      à                                                                                                                          (vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           4                        +                  power-domain@16          ý         8  ®      â      $      %      &      '      (      )      D  (vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         4                        +                  power-domain@17          ý           ®      á                    (vppsys1 vppsys1-0 vppsys1-1         4                     power-domain@22          ý            ®                              $  (wepsys-0 wepsys-1 wepsys-2 wepsys-3         4                     power-domain@23          ý           ®               (vdec0-0         4                        +                   power-domain@24          ý           ®               (vdec1-0         4                     power-domain@25          ý           ®                (vdec2-0         4                        power-domain@26          ý           ®   !            (venc0-larb          4                        +                   power-domain@27          ý           ®   "            (venc1-larb          4                        power-domain@18          ý            ®      ã   #       #      #         &  (vdosys1 vdosys1-0 vdosys1-1 vdosys1-2           4                        +                  power-domain@19          ý           4                     power-domain@20          ý           4                     power-domain@21          ý           ®      Q        (hdmi_tx                      power-domain@28          ý           ®   $       $   
        (img-0 img-1         4                        +                  power-domain@29          ý                     power-domain@30          ý           ®         $      %           (ipe ipe-0 ipe-1         4                        power-domain@31          ý         (  ®   &       &      &      &      &           (cam-0 cam-1 cam-2 cam-3 cam-4           4                        +                  power-domain@32          ý                      power-domain@33          ý   !                  power-domain@34          ý   "                           power-domain@0           ý            4                     power-domain@1           ý           4                     power-domain@2           ý                     power-domain@3           ý                     power-domain@4           ý           ®      5      7        (csi_rx_top csi_rx_top1                    power-domain@5           ý           ®   '           (ether                     power-domain@6           ý           ®      X      n        (adsp adsp1                       +            4                 power-domain@7           ý            ®      g      "      n      2        (audio audio1 audio2 audio3          4                              watchdog@10007000             mediatek,mt8195-wdt          F         ý     p                o           Î   -      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon            ý     À                ¡           Î         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer          ý    p                [      	               ®   (      pwrap@10024000            mediatek,mt8195-pwrap syscon             ý    @                |pwrap           [       ó               ®                   	  (spi wrap            ^      $        n      Ë   pmic              mediatek,mt6359          Q        )           …      Þ      adc           mediatek,mt6359-auxadc          ™         mt6359codec       regulators            mediatek,mt6359-regulator      buck_vs1            «vs1         º 5         Ò !‘À        ê                   buck_vgpu11         «vgpu11          º €        Ò 7          ˆ        ê   È        /                         buck_vmodem         «vmodem          º €        Ò Èà          *        ê   È      buck_vpu            «vpu         º €        Ò 7          ˆ        ê   È        /                         buck_vcore          «vcore           º €        Ò Ö           ˆ        ê   È        /                         buck_vs2            «vs2         º 5         Ò j         ê                   buck_vpa            «vpa         º ¡         Ò 7±Ð        ê  ,      buck_vproc2         «vproc2          º €        Ò 7          L        ê   È        /                         buck_vproc1         «vproc1          º €        Ò 7          L        ê   È        /                         buck_vcore_sshub            «vcore_sshub         º €        Ò 7      buck_vgpu11_sshub           «vgpu11_sshub            º €        Ò 7      ldo_vaud18          «vaud18          º w@        Ò w@        ê   ð      ldo_vsim1           «vsim1           º ð         Ò /M`      ldo_vibr            «vibr            º O€        Ò 2Z       ldo_vrf12           «vrf12           º Èà        Ò Ö                ldo_vusb            «vusb            º -ÆÀ        Ò -ÆÀ        ê  À                 Î   <      ldo_vsram_proc2         «vsram_proc2         º ¡         Ò ½¶          L        ê   ð               ldo_vio18           «vio18           º ð         Ò ýà        ê  À               ldo_vcamio          «vcamio          º ð         Ò ýà      ldo_vcn18           «vcn18           º w@        Ò w@        ê   ð      ldo_vfe28           «vfe28           º *¹€        Ò *¹€        ê   x      ldo_vcn13           «vcn13           º »         Ò Ö       ldo_vcn33_1_bt          «vcn33_1_bt          º *¹€        Ò 5gà      ldo_vcn33_1_wifi            «vcn33_1_wifi            º *¹€        Ò 5gà      ldo_vaux18          «vaux18          º w@        Ò w@        ê   ð               ldo_vsram_others            «vsram_others            º ¡         Ò ½¶          ˆ        ê   ð               ldo_vefuse          «vefuse          º ð         Ò „€      ldo_vxo22           «vxo22           º w@        Ò !‘À               ldo_vrfck           «vrfck           º ã`        Ò ð       ldo_vrfck_1         «vrfck           º ëÀ        Ò j       ldo_vbif28          «vbif28          º *¹€        Ò *¹€        ê   ð      ldo_vio28           «vio28           º *¹€        Ò 2Z                ldo_vemc            «vemc            º ,@         Ò 2Z       ldo_vemc_1          «vemc            º &%         Ò 2Z         Î   @      ldo_vcn33_2_bt          «vcn33_2_bt          º *¹€        Ò 5gà      ldo_vcn33_2_wifi            «vcn33_2_wifi            º *¹€        Ò 5gà      ldo_va12            «va12            º O€        Ò Ö                ldo_va09            «va09            º 5         Ò O€      ldo_vrf18           «vrf18           º ð         Ò žP      ldo_vsram_md          	  «vsram_md            º ¡         Ò ½¶          *        ê   ð               ldo_vufs            «vufs            º ð         Ò ýà        Î   A      ldo_vm18            «vm18            º ð         Ò ýà               ldo_vbbck           «vbbck           º Èà        Ò O€               ldo_vsram_proc1         «vsram_proc1         º ¡         Ò ½¶          L        ê   ð               ldo_vsim2           «vsim2           º ð         Ò /M`      ldo_vsram_others_sshub          «vsram_others_sshub          º ¡         Ò ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi              ý    p            �                |pmif spmimst            ®                   E      (  (pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         ^      $        n      Ë      infra-iommu@10315000              mediatek,mt8195-iommu-infra          ý    1P       P       P  [                                                                         G           Î   J      mailbox@10320000              mediatek,mt8195-gce          ý    2        @         [       â               T           ®              Î   ƒ      mailbox@10330000              mediatek,mt8195-gce          ý    3        @         [       ä               T           ®              Î   a      scp@10500000              mediatek,mt8195-scp       0   ý    P             r             p        €         |sram cfg l1tcm          [      Î             	  kdisabled            Î   b      clock-controller@10720000             mediatek,mt8195-scp_adsp             ý    r                 ¡           Î   )      dsp@10803000              mediatek,mt8195-dsp           ý    €0            „               	  |cfg sram          ,  ®      X         n      Š   )          #      K  (adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          `   *           nrx tx           y   +   ,      	  kdisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           T             ý    �`                [      ¾               Î   +      mailbox@10817000              mediatek,mt8195-adsp-mbox           T             ý    �p                [      ¿               Î   ,      mt8195-afe-pcm@10890000           mediatek,mt8195-audio            ý    ‰                 €           `   *           [      6               ’   -         	  ™audiosys          ”  ®                     Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d      2   )          ó  (clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  kdisabled            Î         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [       �               ®               	  (baud bus            kokay            ¥default         ³   .      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [       Ž               ®               	  (baud bus            kokay            ¥default         ³   /      serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [       �               ®               	  (baud bus          	  kdisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [      Ó               ®               	  (baud bus          	  kdisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [      Ô               ®               	  (baud bus          	  kdisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [      Õ               ®               	  (baud bus          	  kdisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc            ý                      ®              (main            ™         	  kdisabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon            ý     0                ¡           Î   '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý                      [       ¿               ®      ™                    (parent-clk sel-clk spi-clk        	  kdisabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap          ý     °                [       ©               ®              ’               ½   0   1      $  Élvts-calib-data-1 lvts-calib-data-2         Ú           Î   ž      svs@1100bc00              mediatek,mt8195-svs          ý     ¼                [       Ç               ®              (main            ½   2   0      (  Ésvs-calibration-data t-calibration-data         ’              ™svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm            ý     à                [       Ë               `   *           ð           ®      *      0        (main mm       	  kdisabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm            ý     ð                [                     ð           ®      +      N        (main mm       	  kdisabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý                     [       À               ®      ™            3        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý                     [       Á               ®      ™            4        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý    0                [       Â               ®      ™            5        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý    €                [       Ã               ®      ™            <        (parent-clk sel-clk spi-clk        	  kdisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý    �                [       Ä               ®      ™            =        (parent-clk sel-clk spi-clk        	  kdisabled          spi@1101d000              mediatek,mt8195-spi-slave            ý    Ð                [       Å               ®      R        (spi         ^              n      ˜      	  kdisabled          spi@1101e000              mediatek,mt8195-spi-slave            ý    à                [       Æ               ®      S        (spi         ^              n      ˜      	  kdisabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a            ý           @         [      Ì               ûmacirq        .  (axi apb mac_main ptp_ref rmii_internal mac_cg         0  ®   '       '         R      S      T   '           ^      R      S      T        n      Â      Ã      Ä        `   *                         3        ,   4        ?   5        R           ]           h            kokay          	  urgmii-id            ~   6        ‰      ]            ™      ' 8€        ¥default sleep           ³   7        ®   8   mdio              snps,dwmac-mdio                      +       ethernet-phy@1           ý           Î   6         stmmac-axi-config           ¸           È           Ø                                 Î   3      rx-queues-config            â            ø        Î   4   queue0           	                  queue1           	                  queue2           	                  queue3           	                     tx-queues-config            4            J        Î   5   queue0          \            	        h          queue1          \            	        h         queue2          \            	        h         queue3          \            	        h               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3            ý            -ÿ     >              	  |mac ippc                                 ?                      +           [       €               ®      /      í      B        (sys_ck ref_ck mcu_ck            v   9      :            {        ‰   ;      g        kokay                <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci           ý                       |mac         [       �               ^      ,      -        n      –      –      $  ®      /      í               B      $  (sys_ck ref_ck mcu_ck dma_ck xhci_ck         kokay            ®   =         mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           ý    #             õ                 [       ƒ               ®                          (source hclk source_cg           kokay            ¥default state_uhs           ³   >        ®   ?        º           ÄëÂ          Ò         ä         ó                                   ! L        0   @        <   A         I      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           ý    $             Ç                 [       ‡               ®                  $        (source hclk source_cg           ^              n      ¿        kokay            ¥default state_uhs           ³   B        ®   C        W      �           º           ÄëÂ          `         q         ~        0   D        <   E      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           ý    %             æ                 [       ˆ               ®                   I        (source hclk source_cg           ^               n      ¿      	  kdisabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu             ý    '€                [       ª               ®              ’              ½   0   1      $  Élvts-calib-data-1 lvts-calib-data-2         Ú           Î   •      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci            ý    )             )>              	  |mac ippc            [                     v   F      G           ^      .      /        n      –      –      $  ®   '         ï            '         $  (sys_ck ref_ck mcu_ck dma_ck xhci_ck         ‰   ;      h         {        kokay                <      usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3            ý    *       -ÿ    *>              	  |mac ippc                        *        ?                      +           [                     ^      0        n      –        ®   '         ñ   '           (sys_ck ref_ck mcu_ck            v   H            {        ‰   ;      i        kokay                <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci           ý                       |mac         [                     ^      1        n      –        ®   '           (sys_ck          kokay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3            ý    +       -ÿ    +>              	  |mac ippc                        +        ?                      +           [                     ^      2        n      –        ®   '         ó   '   	        (sys_ck ref_ck mcu_ck            v   I            {        ‰   ;      j        kokay                <   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci           ý                       |mac         [                     ^      3        n      –        ®   '   	        (sys_ck          kokay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            ñpci                      +            ý    /        @       	  |pcie-mac            [                     Œ       ÿ      8  �                           ‚                       à          –       J                         0  ®      V      #      &      +      K   '         /  (pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ^      G        n              v   K      	  ¯pcie-phy            `   *            )           ¹                     `  Ì                  L                      L                     L                     L         	  kdisabled       interrupt-controller             Q                     )           Î   L         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            ñpci                      +            ý    /€       @       	  |pcie-mac            [                     Œ       ÿ      8  �       $       $           ‚       $       $       à          –       J                         (  ®      W         X         Q   '         /  (pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          ^      H        n              v   G         	  ¯pcie-phy            `   *           )           ¹                     `  Ì                  M                      M                     M                     M         	  kdisabled       interrupt-controller             Q                     )           Î   M         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor          ý    2À                [      9               ®      o   '      '           (spi sf axi                       +          	  kdisabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse             ý    Á                              +      usb3-tx-imp@184,1            ý  „           Ú               Î   W      usb3-rx-imp@184,2            ý  „           Ú              Î   V      usb3-intr@185            ý  …           Ú              Î   U      usb3-tx-imp@186,1            ý  †           Ú               Î   T      usb3-rx-imp@186,2            ý  †           Ú              Î   S      usb3-intr@187            ý  ‡           Ú              Î   R      usb2-intr-p0@188,1           ý  ˆ           Ú             usb2-intr-p1@188,2           ý  ˆ           Ú            usb2-intr-p2@189,1           ý  ‰           Ú            usb2-intr-p3@189,2           ý  ‰           Ú            pciephy-rx-ln1@190,1             ý  �           Ú               Î   ^      pciephy-tx-ln1-nmos@190,2            ý  �           Ú              Î   ]      pciephy-tx-ln1-pmos@191,1            ý  ‘           Ú               Î   \      pciephy-rx-ln0@191,2             ý  ‘           Ú              Î   [      pciephy-tx-ln0-nmos@192,1            ý  ’           Ú               Î   Z      pciephy-tx-ln0-pmos@192,2            ý  ’           Ú              Î   Y      pciephy-glb-intr@193             ý  “           Ú               Î   X      dp-data@1ac          ý  ¬           Î   ”      lvts1-calib@1bc          ý  ¼           Î   0      lvts2-calib@1d0          ý  Ð   8        Î   1      svs-calib@580            ý  €   d        Î   2      socinfo-data1@7a0            ý               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   Ä             kokay       usb-phy@0            ý               ®      ò        (ref         ß           Î   H         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   Å             kokay       usb-phy@0            ý               ®      ô        (ref         ß           Î   I         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx          ý    È                 ®           Êmipi_tx0_pll            ¡            ß          	  kdisabled            Î   „      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx          ý    É                 ®           Êmipi_tx1_pll            ¡            ß          	  kdisabled            Î   …      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    Ð             "€       €        [       š               µ           ®   N          ;      	  (main dma                         +          	  kdisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    Ð            "        €        [       ›               µ           ®   N         ;      	  (main dma                         +            kokay            # €        ³   O        ¥default    pmic@34           mediatek,mt6360          ý   4         Q        )           …      e           ûIRQB       charger           mediatek,mt6360-chg         ê Ý@    usb-otg-vbus-regulator          «usb-otg-vbus            º C…(        Ò Xáè        Î   =         regulator             mediatek,mt6360-regulator           	   P   buck1           «mt6360,buck1            º “à        Ò Ö         /                         buck2           «mt6360,buck2            º “à        Ò Ö         /                           Î   P      ldo1            «mt6360,ldo1         º O€        Ò 6î€        /             ldo2            «mt6360,ldo2         º O€        Ò 6î€        /             ldo3            «mt6360,ldo3         º O€        Ò 6î€        /               Î   E      ldo5            «mt6360,ldo5         º )2à        Ò 6î€        /               Î   D      ldo6            «mt6360,ldo6         º ¡         Ò           /             ldo7            «mt6360,ldo7         º ¡         Ò           /                               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    Ð             "€       €        [       œ               µ           ®   N         ;      	  (main dma                         +          	  kdisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s           ý    Ð0                ¡           Î   N      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à             " €       €        [       �               µ           ®   Q          ;      	  (main dma                         +          	  kdisabled          i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à            "        €        [       “               µ           ®   Q         ;      	  (main dma                         +          	  kdisabled          i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à             "€       €        [       –               µ           ®   Q         ;      	  (main dma                         +          	  kdisabled          i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à0            "€       €        [       ˜               µ           ®   Q         ;      	  (main dma                         +          	  kdisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à@            "        €        [       ™               µ           ®   Q         ;      	  (main dma                         +          	  kdisabled          clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w           ý    àP                ¡           Î   Q      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   ã             `   *           kokay       usb-phy@0            ý               ®      ð           (ref da_ref          ß           Î   F      usb-phy@700          ý              ®            ð        (ref da_ref          ½   R   S   T        Éintr rx_imp tx_imp          ß           Î   G         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   ä             kokay       usb-phy@0            ý               ®      î           (ref da_ref          ß           Î   9      usb-phy@700          ý              ®            î        (ref da_ref          ½   U   V   W        Éintr rx_imp tx_imp          ß           Î   :         phy@11e80000              mediatek,mt8195-pcie-phy             ý    è                 |sif         ½   X   Y   Z   [   \   ]   ^      G  Églb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          `   *           ß          	  kdisabled            Î   K      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy            ý    ú        À         ®            
  (unipro mp           ß          	  kdisabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm            ý             @         ®   _          0  [      �             Œ             ‹               ûjob mmu gpu         	   `      (  `   *   
   *      *      *      *           	'core0 core1 core2 core3 core4         	  kdisabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg           ý    ûð                ¡           Î   _      syscon@14000000           mediatek,mt8195-vppsys0 syscon           ý                      ¡           	:   a                   Î         dma-controller@14001000           mediatek,mt8195-mdp3-rdma            ý                     	:   a                  	R              	f   b        `   *           	s   c   €        ®            <  y   a         a         a         a         a              	z         display@14002000              mediatek,mt8195-mdp3-fg          ý                      	:   a                   ®             display@14003000              mediatek,mt8195-mdp3-stitch          ý     0                	:   a      0            ®            display@14004000              mediatek,mt8195-mdp3-hdr             ý     @                	:   a      @            ®      "      display@14005000              mediatek,mt8195-mdp3-aal             ý     P                [      F               	:   a      P            ®      
        `   *         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý     `                	:   a      `            	R    %        ®            display@14007000              mediatek,mt8195-mdp3-tdshp           ý     p                	:   a      p            ®      #      display@14008000              mediatek,mt8195-mdp3-color           ý     €                [      I               	:   a      €            ®      $        `   *         display@14009000              mediatek,mt8195-mdp3-ovl             ý     �                [      J               	:   a      �            ®      %        `   *           	s   c   ‚      display@1400a000              mediatek,mt8195-mdp3-padding             ý                      	:   a                   ®              `   *         display@1400b000              mediatek,mt8195-mdp3-tcc             ý     °                	:   a      °            ®            dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý     À                	:   a      À            	R    +        ®              	s   c   ƒ        `   *           	z         mutex@1400f000            mediatek,mt8195-vpp-mutex            ý     ð                [      P               	:   a      ð            ®              `   *         smi@14010000              mediatek,mt8195-smi-sub-common           ý                     ®                          (apb smi gals0           	…   d        `   *           Î   e      smi@14011000              mediatek,mt8195-smi-sub-common           ý                    ®                          (apb smi gals0           	…   d        `   *           Î   ‚      smi@14012000              mediatek,mt8195-smi-common-vpp           ý                      ®                                (apb smi gals0 gals1         `   *           Î   d      larb@14013000             mediatek,mt8195-smi-larb             ý    0                	’           	…   e        ®                    (apb smi         `   *           Î   h      iommu@14018000            mediatek,mt8195-iommu-vpp            ý    €              8  	£   f   g   h   i   j   k   l   m   n   o   p   q   r   s        [      R               ®              (bclk            G           `   *           Î   c      clock-controller@14e00000             mediatek,mt8195-wpesys           ý    à                 ¡           Î         clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0          ý    à                 ¡         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1          ý    à0                ¡         larb@14e04000             mediatek,mt8195-smi-larb             ý    à@                	’           	…   t        ®                    (apb smi         `   *           Î   ‰      larb@14e05000             mediatek,mt8195-smi-larb             ý    àP                	’           	…   d        ®                          (apb smi gals            `   *           Î   j      syscon@14f00000           mediatek,mt8195-vppsys1 syscon           ý    ð                 ¡           	:   a   	               Î         mutex@14f01000            mediatek,mt8195-vpp-mutex            ý    ð                [      {               	:   a   	              ®      '        `   *         larb@14f02000             mediatek,mt8195-smi-larb             ý    ð                 	’           	…   t        ®                          (apb smi gals            `   *           Î   ˆ      larb@14f03000             mediatek,mt8195-smi-larb             ý    ð0                	’           	…   e        ®                          (apb smi gals            `   *           Î   i      display@14f06000              mediatek,mt8195-mdp3-split           ý    ð`                	:   a   	  `            ®            +      ,        `   *         display@14f07000              mediatek,mt8195-mdp3-tcc             ý    ðp                	:   a   	  p            ®            dma-controller@14f08000           mediatek,mt8195-mdp3-rdma            ý    ð€                	:   a   	  €            	R  „  ¨        ®              	s   u            `   *           	z         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma            ý    ð�                	:   a   	  �            	R  …  ©        ®      
        	s   u   ¤        `   *           	z         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma            ý    ð                 	:   a   	               	R  †  ª        ®              	s   c   À        `   *           	z         display@14f0b000              mediatek,mt8195-mdp3-fg          ý    ð°                	:   a   	  °            ®      	      display@14f0c000              mediatek,mt8195-mdp3-fg          ý    ðÀ                	:   a   	  À            ®            display@14f0d000              mediatek,mt8195-mdp3-fg          ý    ðÐ                	:   a   	  Ð            ®            display@14f0e000              mediatek,mt8195-mdp3-hdr             ý    ðà                	:   a   	  à            ®            display@14f0f000              mediatek,mt8195-mdp3-hdr             ý    ðð                	:   a   	  ð            ®            display@14f10000              mediatek,mt8195-mdp3-hdr             ý    ñ                 	:   a   
               ®             display@14f11000              mediatek,mt8195-mdp3-aal             ý    ñ                [      i               	:   a   
              ®              `   *         display@14f12000              mediatek,mt8195-mdp3-aal             ý    ñ                 [      j               	:   a   
               ®              `   *         display@14f13000              mediatek,mt8195-mdp3-aal             ý    ñ0                [      k               	:   a   
  0            ®      !        `   *         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý    ñ@                	:   a   
  @            	R  �  ¯        ®            display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý    ñP                	:   a   
  P            	R  ‘  °        ®      $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý    ñ`                	:   a   
  `            	R  ’  ±        ®      %      display@14f17000              mediatek,mt8195-mdp3-tdshp           ý    ñp                	:   a   
  p            ®            display@14f18000              mediatek,mt8195-mdp3-tdshp           ý    ñ€                	:   a   
  €            ®      (      display@14f19000              mediatek,mt8195-mdp3-tdshp           ý    ñ�                	:   a   
  �            ®      )      display@14f1a000              mediatek,mt8195-mdp3-merge           ý    ñ                 	:   a   
               ®              `   *         display@14f1b000              mediatek,mt8195-mdp3-merge           ý    ñ°                	:   a   
  °            ®              `   *         display@14f1c000              mediatek,mt8195-mdp3-color           ý    ñÀ                [      t               	:   a   
  À            ®              `   *         display@14f1d000              mediatek,mt8195-mdp3-color           ý    ñÐ                	:   a   
  Ð            [      u               ®              `   *         display@14f1e000              mediatek,mt8195-mdp3-color           ý    ñà                [      v               	:   a   
  à            ®              `   *         display@14f1f000              mediatek,mt8195-mdp3-ovl             ý    ñð                [      w               	:   a   
  ð            ®               `   *           	s   u   ¢      display@14f20000              mediatek,mt8195-mdp3-padding             ý    ò                 	:   a                  ®              `   *         display@14f21000              mediatek,mt8195-mdp3-padding             ý    ò                	:   a                 ®              `   *         display@14f22000              mediatek,mt8195-mdp3-padding             ý    ò                 	:   a                  ®              `   *         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý    ò0                	:   a     0            	R  Ÿ  «        ®              	s   u   £        `   *           	z         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý    ò@                	:   a     @            	R     ¬        ®              	s   u   ¦        `   *           	z         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý    òP                	:   a     P            	R  ¡  ­        ®              	s   c   Â        `   *           	z         clock-controller@15000000             mediatek,mt8195-imgsys           ý                      ¡           Î   $      larb@15001000             mediatek,mt8195-smi-larb             ý                     	’   	        	…   v        ®   $       $       $   
        (apb smi gals            `   *           Î   Š      smi@15002000              mediatek,mt8195-smi-sub-common           ý                      ®   $      $                 (apb smi gals0           	…   d        `   *           Î   y      smi@15003000              mediatek,mt8195-smi-sub-common           ý     0                ®   $       $       $   
        (apb smi gals0           	…   t        `   *           Î   v      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top          ý                     ¡           Î   w      larb@15120000             mediatek,mt8195-smi-larb             ý                     	’   
        	…   v        ®   $      w            (apb smi         `   *           Î   ‹      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr           ý                     ¡         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe          ý    "                 ¡           Î   x      larb@15230000             mediatek,mt8195-smi-larb             ý    #                 	’           	…   v        ®   $      x            (apb smi         `   *           Î   Œ      clock-controller@15330000             mediatek,mt8195-ipesys           ý    3                 ¡           Î   %      larb@15340000             mediatek,mt8195-smi-larb             ý    4                 	’           	…   y        ®   %      %           (apb smi         `   *           Î   k      clock-controller@16000000             mediatek,mt8195-camsys           ý                      ¡           Î   &      larb@16001000             mediatek,mt8195-smi-larb             ý                     	’           	…   z        ®   &       &       &           (apb smi gals            `   *           Î   �      larb@16002000             mediatek,mt8195-smi-larb             ý                      	’           	…   {        ®   &      &           (apb smi         `   *           Î   l      smi@16004000              mediatek,mt8195-smi-sub-common           ý     @                ®   &       &       &           (apb smi gals0           	…   t        `   *           Î   z      smi@16005000              mediatek,mt8195-smi-sub-common           ý     P                ®   &      &                 (apb smi gals0           	…   d        `   *           Î   {      larb@16012000             mediatek,mt8195-smi-larb             ý                     	’           	…   {        ®   |       |            (apb smi         `   *            Î   m      larb@16013000             mediatek,mt8195-smi-larb             ý    0                	’           	…   z        ®   }       }            (apb smi         `   *            Î   Ž      larb@16014000             mediatek,mt8195-smi-larb             ý    @                	’           	…   {        ®   ~       ~            (apb smi         `   *   !        Î   s      larb@16015000             mediatek,mt8195-smi-larb             ý    P                	’           	…   z        ®                      (apb smi         `   *   !        Î   “      clock-controller@1604f000             mediatek,mt8195-camsys_rawa          ý    ð                ¡           Î   |      clock-controller@1606f000             mediatek,mt8195-camsys_yuva          ý    ð                ¡           Î   }      clock-controller@1608f000             mediatek,mt8195-camsys_rawb          ý    ð                ¡           Î   ~      clock-controller@160af000             mediatek,mt8195-camsys_yuvb          ý    
ð                ¡           Î         clock-controller@16140000             mediatek,mt8195-camsys_mraw          ý                     ¡           Î   €      larb@16141000             mediatek,mt8195-smi-larb             ý                    	’           	…   z        ®   &       €       &           (apb smi gals            `   *   "        Î   ’      larb@16142000             mediatek,mt8195-smi-larb             ý                     	’           	…   {        ®   €       €            (apb smi         `   *   "        Î   r      clock-controller@17200000             mediatek,mt8195-ccusys           ý                      ¡           Î   �      larb@17201000             mediatek,mt8195-smi-larb             ý                     	’           	…   {        ®   �       �            (apb smi         `   *           Î   n      video-codec@18000000              mediatek,mt8195-vcodec-dec          	f   b        	s   u                        +             ý                   @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc          ý                       	s   c  à   c  á         ®      A                  �        (sel vdec lat top            ^      A        n      �        `   *         video-codec@10000             mediatek,mtk-vcodec-lat          ý                      [      Ä             0  	s   u      u     u     u     u     u           ®      A                  �        (sel vdec lat top            ^      A        n      �        `   *         video-codec@25000             mediatek,mtk-vcodec-core             ý     P                [      Ã             P  	s   u      u  ¡   u  ¢   u  £   u  ¤   u  ¥   u  ¦   u  §   u  ¨   u  ©         ®      A                  �        (sel vdec lat top            ^      A        n      �        `   *            larb@1800d000             mediatek,mt8195-smi-larb             ý     Ð                	’           	…   t        ®                      (apb smi         `   *           Î   ‘      larb@1800e000             mediatek,mt8195-smi-larb             ý     à                	’           	…   ‚        ®                     (apb smi         `   *           Î   q      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc          ý     ð                ¡           Î         larb@1802e000             mediatek,mt8195-smi-larb             ý    à                	’           	…   t        ®                      (apb smi         `   *           Î   �      clock-controller@1802f000             mediatek,mt8195-vdecsys          ý    ð                ¡           Î         larb@1803e000             mediatek,mt8195-smi-larb             ý    à                	’           	…   ‚        ®                      (apb smi         `   *           Î   p      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1            ý    ð                ¡           Î          clock-controller@190f3000             mediatek,mt8195-apusys_pll           ý    0                ¡         clock-controller@1a000000             mediatek,mt8195-vencsys          ý                      ¡           Î   !      larb@1a010000             mediatek,mt8195-smi-larb             ý                     	’           	…   t        ®   !      !           (apb smi         `   *           Î   �      video-codec@1a020000              mediatek,mt8195-vcodec-enc           ý                   H  	s   u  `   u  a   u  b   u  c   u  d   u  v   u  w   u  x   u  y        [      U               	f   b        ®   !         	  (venc_sel            ^      @        n      �        `   *                        +         jpgdec-master             mediatek,mt8195-jpgdec          `   *         0  	s   u  m   u  n   u  r   u  s   u  t   u  u                     +               jpgdec@1a040000           mediatek,mt8195-jpgdec-hw            ý                   0  	s   u  m   u  n   u  r   u  s   u  t   u  u        [      W               ®   !           (jpgdec          `   *         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw            ý                   0  	s   u  m   u  n   u  r   u  s   u  t   u  u        [      X               ®   !           (jpgdec          `   *         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw            ý                   0  	s   c  �   c  Ž   c  ’   c  “   c  ”   c  •        [      \               ®   "           (jpgdec          `   *            clock-controller@1b000000             mediatek,mt8195-vencsys_core1            ý                      ¡           Î   "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon             ý                     y   ƒ               ¡           	:   ƒ                  Î         jpgenc-master             mediatek,mt8195-jpgenc          `   *            	s   c  ‡   c  ˆ   c  ‰   c  Œ                     +               jpgenc@1a030000           mediatek,mt8195-jpgenc-hw            ý                      	s   u  g   u  h   u  i   u  l        [      V               ®   !           (jpgenc          `   *         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw            ý                      	s   c  ‡   c  ˆ   c  ‰   c  Œ        [      [               ®   "           (jpgenc          `   *            larb@1b010000             mediatek,mt8195-smi-larb             ý                     	’           	…   d        ®   "      "                  (apb smi gals            `   *           Î   o      ovl@1c000000              mediatek,mt8195-disp-ovl             ý                      [      |               `   *           ®               	s   u           	:   ƒ                rdma@1c002000             mediatek,mt8195-disp-rdma            ý                      [      ~               `   *           ®              	s   u            	:   ƒ                color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color            ý     0                [                     `   *           ®              	:   ƒ     0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr            ý     @                [      €               `   *           ®              	:   ƒ     @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal            ý     P                [      �               `   *           ®              	:   ƒ     P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma            ý     `                [      ‚               `   *           ®              	:   ƒ     `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither          ý     p                [      ƒ               `   *           ®      	        	:   ƒ     p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi          ý     €                [      „               `   *           ®            *   „        (engine digital hs           v   „        ¯dphy          	  kdisabled          dsc@1c009000              mediatek,mt8195-disp-dsc             ý     �                [      …               `   *           ®              	:   ƒ     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi          ý                     [      Ž               `   *           ®            +   …        (engine digital hs           v   …        ¯dphy          	  kdisabled          merge@1c014000            mediatek,mt8195-disp-merge           ý    @                [      �               `   *           ®              	:   ƒ     @          dp-intf@1c015000              mediatek,mt8195-dp-intf          ý    P                [      ‘               ®      ,                    (pixel engine pll          	  kdisabled          mutex@1c016000            mediatek,mt8195-disp-mutex           ý    `                [      ’               `   *           ®              	:   ƒ     `            	R  U      larb@1c018000             mediatek,mt8195-smi-larb             ý    €                	’            	…   t        ®      (      (              (apb smi gals            `   *           Î   †      larb@1c019000             mediatek,mt8195-smi-larb             ý    �                	’           	…   d        ®      (                     (apb smi gals            `   *           Î   f      syscon@1c100000           mediatek,mt8195-vdosys1 syscon           ý                     y   ƒ              	:   ƒ                  ¡           o           Î   #      smi@1c01b000              mediatek,mt8195-smi-common-vdo           ý    °                 ®      %      &      )      $        (apb smi gals0 gals1         `   *           Î   t      iommu@1c01f000            mediatek,mt8195-iommu-vdo            ý    ð              8  	£   †   ‡   ˆ   ‰   Š   ‹   Œ   �   Ž   �   �   ‘   ’   “        [      �               G           ®      '        (bclk            `   *           Î   u      mutex@1c101000            mediatek,mt8195-disp-mutex           ý                    [      î               `   *           ®   #           	:   ƒ                 	R  À      larb@1c102000             mediatek,mt8195-smi-larb             ý                     	’           	…   t        ®   #       #       #           (apb smi gals            `   *           Î   ‡      larb@1c103000             mediatek,mt8195-smi-larb             ý    0                	’           	…   d        ®   #      #                  (apb smi gals            `   *           Î   g      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma            ý    @                [      ï               ®   #           `   *           	s   u   @        	:   ƒ     @            	z         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma            ý    P                [      ð               ®   #           `   *           	s   c   `        	:   ƒ     P            	z         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma            ý    `                [      ñ               ®   #           `   *           	s   u   A        	:   ƒ     `            	z         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma            ý    p                [      ò               ®   #           `   *           	s   c   a        	:   ƒ     p            	z         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma            ý    €                [      ó               ®   #           `   *           	s   u   B        	:   ƒ     €            	z         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma            ý    �                [      ô               ®   #           `   *           	s   c   b        	:   ƒ     �            	z         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma            ý                     [      õ               ®   #           `   *           	s   u   C        	:   ƒ                  	z         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma            ý    °                [      ö               ®   #           `   *           	s   c   c        	:   ƒ     °            	z         vpp-merge@1c10c000            mediatek,mt8195-disp-merge           ý    À                [      ÷               ®   #   	   #           (merge merge_async           `   *           	:   ƒ     À             	²        ’   #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge           ý    Ð                [      ø               ®   #   
   #           (merge merge_async           `   *           	:   ƒ     Ð             	²        ’   #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge           ý    à                [      ù               ®   #      #           (merge merge_async           `   *           	:   ƒ     à             	²        ’   #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge           ý    ð                [      ú               ®   #      #           (merge merge_async           `   *           	:   ƒ     ð             	²        ’   #         vpp-merge@1c110000            mediatek,mt8195-disp-merge           ý                     [      û               ®   #      #           (merge merge_async           `   *           	:   ƒ                   	Æ        ’   #         dp-intf@1c113000              mediatek,mt8195-dp-intf          ý    0                [                     `   *           ®   #   /   #                 (pixel engine pll          	  kdisabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p   ý    @            P            p            �                         °            À              4  |mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  	:   ƒ     @       ƒ     P       ƒ     p       ƒ     �       ƒ             ƒ     °       ƒ     À          h  ®   #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *            ƒ  (mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          `   *           	s   c   d   c   e        [                   (  ’   #   3   #   4   #   5   #   6   #   7      E  ™vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx           ý    P        €         ½   ”        Édp_calibration_data         `   *           [      ¤               	Ý  ¤      	  kdisabled          dp-tx@1c600000            mediatek,mt8195-dp-tx            ý    `        €         ½   ”        Édp_calibration_data         `   *           [      Ê               	Ý  ¤      	  kdisabled             thermal-zones      cpu0-thermal            	î  è        	ü   ú        
   •      trips      trip-alert          
" L        
.  Ð         øpassive         Î   –      trip-crit           
" †         
.  Ð      	   øcritical             cooling-maps       map0            
9   –      0  
>   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            	î  è        	ü   ú        
   •      trips      trip-alert          
" L        
.  Ð         øpassive         Î   —      trip-crit           
" †         
.  Ð      	   øcritical             cooling-maps       map0            
9   —      0  
>   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            	î  è        	ü   ú        
   •      trips      trip-alert          
" L        
.  Ð         øpassive         Î   ˜      trip-crit           
" †         
.  Ð      	   øcritical             cooling-maps       map0            
9   ˜      0  
>   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            	î  è        	ü   ú        
   •      trips      trip-alert          
" L        
.  Ð         øpassive         Î   ™      trip-crit           
" †         
.  Ð      	   øcritical             cooling-maps       map0            
9   ™      0  
>   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            	î  è        	ü   ú        
   •       trips      trip-alert          
" L        
.  Ð         øpassive         Î   š      trip-crit           
" †         
.  Ð      	   øcritical             cooling-maps       map0            
9   š      0  
>   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            	î  è        	ü   ú        
   •      trips      trip-alert          
" L        
.  Ð         øpassive         Î   ›      trip-crit           
" †         
.  Ð      	   øcritical             cooling-maps       map0            
9   ›      0  
>   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            	î  è        	ü   ú        
   •      trips      trip-alert          
" L        
.  Ð         øpassive         Î   œ      trip-crit           
" †         
.  Ð      	   øcritical             cooling-maps       map0            
9   œ      0  
>   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            	î  è        	ü   ú        
   •      trips      trip-alert          
" L        
.  Ð         øpassive         Î   �      trip-crit           
" †         
.  Ð      	   øcritical             cooling-maps       map0            
9   �      0  
>   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            	î  è        	ü   ú        
   ž      trips      trip-alert          
" L        
.  Ð         øpassive       trip-crit           
" †         
.  Ð      	   øcritical                vpu1-thermal            	î  è        	ü   ú        
   ž   	   trips      trip-alert          
" L        
.  Ð         øpassive       trip-crit           
" †         
.  Ð      	   øcritical                gpu-thermal         	î  è        	ü   ú        
   ž   
   trips      trip-alert          
" L        
.  Ð         øpassive       trip-crit           
" †         
.  Ð      	   øcritical                gpu1-thermal            	î  è        	ü   ú        
   ž      trips      trip-alert          
" L        
.  Ð         øpassive       trip-crit           
" †         
.  Ð      	   øcritical                vdec-thermal            	î  è        	ü   ú        
   ž      trips      trip-alert          
" L        
.  Ð         øpassive       trip-crit           
" †         
.  Ð      	   øcritical                img-thermal         	î  è        	ü   ú        
   ž      trips      trip-alert          
" L        
.  Ð         øpassive       trip-crit           
" †         
.  Ð      	   øcritical                infra-thermal           	î  è        	ü   ú        
   ž      trips      trip-alert          
" L        
.  Ð         øpassive       trip-crit           
" †         
.  Ð      	   øcritical                cam0-thermal            	î  è        	ü   ú        
   ž      trips      trip-alert          
" L        
.  Ð         øpassive       trip-crit           
" †         
.  Ð      	   øcritical                cam1-thermal            	î  è        	ü   ú        
   ž      trips      trip-alert          
" L        
.  Ð         øpassive       trip-crit           
" †         
.  Ð      	   øcritical                   chosen          
Mserial0:921600n8          firmware       optee             linaro,optee-tz         smc          gpio-keys         
    gpio-keys           ¥default         ³   Ÿ   key-0           Z      j         
  
Yvolume_up           
_   s         {        
j            memory@40000000          ñmemory           ý    @                reserved-memory                      +               optee@43200000           
|         ý    C        À        memory@50000000           shared-dma-pool          ý    P       �           
|      memory@53000000           shared-dma-pool          ý    S       @        memory@54600000          
|         ý    T`                memory@60000000           shared-dma-pool          ý    `                  
|      memory@62000000           shared-dma-pool          ý    b       @              	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux drive-strength input-enable output-high input-disable bias-disable bias-pull-up bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle snps,reset-gpio snps,reset-delays-us pinctrl-1 snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup vusb33-supply vbus-supply bus-width max-frequency cap-mmc-highspeed mmc-hs200-1_8v mmc-hs400-1_8v cap-mmc-hw-reset no-sdio no-sd hs400-ds-delay vmmc-supply vqmmc-supply non-removable cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN3-supply operating-points-v2 power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path label linux,code debounce-interval no-map 