Ðþí !    8 ¨   (            X p                             $    mediatek,mt8195-evb mediatek,mt8195                                  +         !   7MediaTek MT8195 evaluation board       aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          ƒ/soc/vpp-merge@1c10f000          Š/soc/vpp-merge@1c110000          ‘/soc/dma-controller@1c104000             œ/soc/dma-controller@1c105000             §/soc/dma-controller@1c106000             ²/soc/dma-controller@1c107000             ½/soc/dma-controller@1c108000             È/soc/dma-controller@1c109000             Ó/soc/dma-controller@1c10a000             Þ/soc/dma-controller@1c10b000             é/soc/serial@11001100          cpus                         +       cpu@0            ñcpu           arm,cortex-a55           ý            psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î   	      cpu@100          ñcpu           arm,cortex-a55           ý           psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î   
      cpu@200          ñcpu           arm,cortex-a55           ý           psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î         cpu@300          ñcpu           arm,cortex-a55           ý           psci                           #ec3@        3  4        F              V  €         c   @        u   €        ‚  €         �   @        ¡   €        ®           ¿           Î         cpu@400          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu@500          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu@600          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu@700          ñcpu           arm,cortex-a78           ý           psci                          #�fÔÀ        3           F              V           c   @        u           ‚           �   @        ¡           ®           ¿           Î         cpu-map    cluster0       core0           Ö   	      core1           Ö   
      core2           Ö         core3           Ö         core4           Ö         core5           Ö         core6           Ö         core7           Ö               idle-states         Úpsci       cpu-retention-l           arm,idle-state          ç           þ           2            _        0  D        Î         cpu-retention-b           arm,idle-state          ç           þ           -            Œ        0  ä        Î         cpu-off-l             arm,idle-state          ç          þ           7            ›        0  H        Î         cpu-off-b             arm,idle-state          ç          þ           2            È        0  è        Î            l2-cache0             cache           A           X           e   @        w           ®            M        Î         l2-cache1             cache           A           X           e   @        w           ®            M        Î         l3-cache              cache           A           X            e   @        w            M        Î            dsu-pmu           arm,dsu-pmu         [                       f   	   
                          kfail          dmic-codec            dmic-codec          r              2      mt8195-sound            �         	  kdisabled          fixed-factor-clock-13m            fixed-factor-clock          ¡            ®           µ           ¿           Êclk13m          Î   (      oscillator-26m            fixed-clock         ¡            #Œº€        Êclk26m          Î         oscillator-32k            fixed-clock         ¡            #  €         Êclk32k        performance-controller@11bc10             mediatek,cpufreq-hw           ý     ¼            ½0               Ý           Î         opp-table-gpu             operating-points-v2          ÷        Î   U   opp-390000000               >í€        	 	‰h      opp-410000000               p€        	 	¡Ò      opp-431000000               °‰À        	 	¡Ò      opp-473000000               1h@        	 	º<      opp-515000000               ²FÀ        	 	º<      opp-556000000               !#ã         	 	Ò¦      opp-598000000               #¤Á€        	 	ë      opp-640000000               &%          	 	ë      opp-670000000               'ïc€        	 
ä      opp-700000000               )¹'         	 
L¸      opp-730000000               +‚ê€        	 
}Œ      opp-760000000               -L®         	 
®`      opp-790000000               /q€        	 
ß4      opp-820000000               0à5         	       opp-850000000               2©ø€        	 @Ü      opp-880000000               4s¼         	 q°         pmu-a55           arm,cortex-a55-pmu                      [                  pmu-a78           arm,cortex-a78-pmu                      [                  psci              arm,psci-1.0            smc       timer             arm,armv8-timer                   @  [                                             
             soc                      +             simple-bus                                             interrupt-controller@c000000              arm,gic-v3          )           :                        Q          ý                                    [      	               Î      ppi-partitions     interrupt-partition-0           f   	   
              Î         interrupt-partition-1           f                    Î               syscon@10000000            mediatek,mt8195-topckgen syscon          ý                      ¡           Î         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon           ý                     ¡           o           Î         syscon@10003000           mediatek,mt8195-pericfg syscon           ý     0                ¡           Î   7      pinctrl@10005000              mediatek,mt8195-pinctrl       €   ý     P            Ñ             Ó             Ô             â             ë             ô              °              B  |iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            †        –           ¢              �         Q        [       ë               )           Î      i2c0-pins           Î   D   pins            ®    	        µ   e        Â            i2c1-pins           Î   E   pins            ®  
          µ   e        Â            i2c4-pins           Î   F   pins            ®            µ   e        Ñ  è         i2c6-pins           Î   B   pins            ®            µ   e         i2c7-pins      pins            ®            µ   e         nor-pins            Î   @   pins0           ®  Ž  �  �         é      pins1           ®  Œ  ‚  ƒ         µ         uart0-pins          Î   .   pins            ®  b  c            syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd             ý     `           power-controller          !    mediatek,mt8195-power-controller                         +            ø           Î   *   power-domain@8           ý                        +            ø      power-domain@9           ý   	        ®                    mfg alt                                 +            ø      power-domain@10          ý   
        ø          power-domain@11          ý           ø          power-domain@12          ý           ø          power-domain@13          ý           ø          power-domain@14          ý           ø                power-domain@15          ý         Ø  ®                        	      @      A      K      à                                                                                                                          vppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18                                   +            ø      power-domain@16          ý         8  ®      â      $      %      &      '      (      )      D  vdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5                                 +            ø      power-domain@17          ý           ®      á                    vppsys1 vppsys1-0 vppsys1-1                    ø          power-domain@22          ý            ®                              $  wepsys-0 wepsys-1 wepsys-2 wepsys-3                    ø          power-domain@23          ý           ®               vdec0-0                                 +            ø       power-domain@24          ý           ®               vdec1-0                    ø          power-domain@25          ý           ®                vdec2-0                    ø             power-domain@26          ý           ®   !            venc0-larb                                  +            ø       power-domain@27          ý           ®   "            venc1-larb                     ø             power-domain@18          ý            ®      ã   #       #      #         &  vdosys1 vdosys1-0 vdosys1-1 vdosys1-2                                   +            ø      power-domain@19          ý                      ø          power-domain@20          ý                      ø          power-domain@21          ý           ®      Q        hdmi_tx         ø             power-domain@28          ý           ®   $       $   
        img-0 img-1                                 +            ø      power-domain@29          ý           ø          power-domain@30          ý           ®         $      %           ipe ipe-0 ipe-1                    ø             power-domain@31          ý         (  ®   &       &      &      &      &           cam-0 cam-1 cam-2 cam-3 cam-4                                   +            ø      power-domain@32          ý            ø          power-domain@33          ý   !        ø          power-domain@34          ý   "        ø                   power-domain@0           ý                       ø          power-domain@1           ý                      ø          power-domain@2           ý           ø          power-domain@3           ý           ø          power-domain@4           ý           ®      5      7        csi_rx_top csi_rx_top1          ø          power-domain@5           ý           ®   '           ether           ø          power-domain@6           ý           ®      X      n        adsp adsp1                       +                       ø      power-domain@7           ý            ®      g      "      n      2        audio audio1 audio2 audio3                     ø                   watchdog@10007000             mediatek,mt8195-wdt          *         ý     p                o           Î   -      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon            ý     À                ¡           Î         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer          ý    p                [      	               ®   (      pwrap@10024000            mediatek,mt8195-pwrap syscon             ý    @                |pwrap           [       ó               ®                   	  spi wrap            B      $        R      Ë      spmi@10027000             mediatek,mt8195-spmi              ý    p            �                |pmif spmimst            ®                   E      (  pmif_sys_ck pmif_tmr_ck spmimst_clk_mux         B      $        R      Ë      infra-iommu@10315000              mediatek,mt8195-iommu-infra          ý    1P       P       P  [                                                                         i           Î   <      mailbox@10320000              mediatek,mt8195-gce          ý    2        @         [       â               v           ®              Î   x      mailbox@10330000              mediatek,mt8195-gce          ý    3        @         [       ä               v           ®              Î   V      scp@10500000              mediatek,mt8195-scp       0   ý    P             r             p        €         |sram cfg l1tcm          [      Î             	  kdisabled            Î   W      clock-controller@10720000             mediatek,mt8195-scp_adsp             ý    r                 ¡           Î   )      dsp@10803000              mediatek,mt8195-dsp           ý    €0            „               	  |cfg sram          ,  ®      X         n      Š   )          #      K  adsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          ‚   *           �rx tx           ›   +   ,      	  kdisabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           v             ý    �`                [      ¾               Î   +      mailbox@10817000              mediatek,mt8195-adsp-mbox           v             ý    �p                [      ¿               Î   ,      mt8195-afe-pcm@10890000           mediatek,mt8195-audio            ý    ‰                 ¢           ‚   *           [      6               ´   -         	  »audiosys          ”  ®                     Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d      2   )          ó  clk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  kdisabled            Î         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [       �               ®               	  baud bus            kokay            Çdefault         Õ   .      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [       Ž               ®               	  baud bus          	  kdisabled          serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [       �               ®               	  baud bus          	  kdisabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [      Ó               ®               	  baud bus          	  kdisabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [      Ô               ®               	  baud bus          	  kdisabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart            ý                     [      Õ               ®               	  baud bus          	  kdisabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc            ý                      ®              main            ß           kokay          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon            ý     0                ¡           Î   '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý                      [       ¿               ®      ™                    parent-clk sel-clk spi-clk        	  kdisabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap          ý     °                [       ©               ®              ´               ñ   /   0      $  ýlvts-calib-data-1 lvts-calib-data-2                    Î   “      svs@1100bc00              mediatek,mt8195-svs          ý     ¼                [       Ç               ®              main            ñ   1   /      (  ýsvs-calibration-data t-calibration-data         ´              »svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm            ý     à                [       Ë               ‚   *           $           ®      *      0        main mm       	  kdisabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm            ý     ð                [                     $           ®      +      N        main mm       	  kdisabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý                     [       À               ®      ™            3        parent-clk sel-clk spi-clk        	  kdisabled          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý                     [       Á               ®      ™            4        parent-clk sel-clk spi-clk        	  kdisabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý    0                [       Â               ®      ™            5        parent-clk sel-clk spi-clk        	  kdisabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý    €                [       Ã               ®      ™            <        parent-clk sel-clk spi-clk        	  kdisabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +             ý    �                [       Ä               ®      ™            =        parent-clk sel-clk spi-clk        	  kdisabled          spi@1101d000              mediatek,mt8195-spi-slave            ý    Ð                [       Å               ®      R        spi         B              R      ˜      	  kdisabled          spi@1101e000              mediatek,mt8195-spi-slave            ý    à                [       Æ               ®      S        spi         B              R      ˜      	  kdisabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a            ý           @         [      Ì               /macirq        .  axi apb mac_main ptp_ref rmii_internal mac_cg         0  ®   '       '         R      S      T   '           B      R      S      T        R      Â      Ã      Ä        ‚   *           ?           P   2        `   3        s   4        †           ‘           œ          	  kdisabled       mdio              snps,dwmac-mdio                      +          stmmac-axi-config           ©           ¹           É                                 Î   2      rx-queues-config            Ó            é        Î   3   queue0           ú                  queue1           ú                  queue2           ú                  queue3           ú                     tx-queues-config            %            ;        Î   4   queue0          M            ú        Y          queue1          M            ú        Y         queue2          M            ú        Y         queue3          M            ú        Y               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3            ý            -ÿ     >              	  |mac ippc                                 ?                      +           [       €               ®      /      í      B        sys_ck ref_ck mcu_ck            g   5      6            l        z   7      g        kokay       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci           ý                       |mac         [       �               B      ,      -        R      –      –      $  ®      /      í               B      $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         kokay             mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           ý    #             õ                 [       ƒ               ®                          source hclk source_cg         	  kdisabled          mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           ý    $             Ç                 [       ‡               ®                  $        source hclk source_cg           B              R      ¿      	  kdisabled          mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc           ý    %             æ                 [       ˆ               ®                   I        source hclk source_cg           B               R      ¿      	  kdisabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu             ý    '€                [       ª               ®              ´              ñ   /   0      $  ýlvts-calib-data-1 lvts-calib-data-2                    Î   Š      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci            ý    )             )>              	  |mac ippc            [                     g   8      9           B      .      /        R      –      –      $  ®   '         ï            '         $  sys_ck ref_ck mcu_ck dma_ck xhci_ck         z   7      h         l        kokay          usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3            ý    *       -ÿ    *>              	  |mac ippc                        *        ?                      +           [                     B      0        R      –        ®   '         ñ   '           sys_ck ref_ck mcu_ck            g   :            l        z   7      i        kokay       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci           ý                       |mac         [                     B      1        R      –        ®   '           sys_ck          kokay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3            ý    +       -ÿ    +>              	  |mac ippc                        +        ?                      +           [                     B      2        R      –        ®   '         ó   '   	        sys_ck ref_ck mcu_ck            g   ;            l        z   7      j        kokay       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci           ý                       |mac         [                     B      3        R      –        ®   '   	        sys_ck          kokay             ‘         pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            ñpci                      +            ý    /        @       	  |pcie-mac            [                     ¢       ÿ      8  �                           ‚                       à          ¬       <              ¶          0  ®      V      #      &      +      K   '         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          B      G        R              g   =      	  Åpcie-phy            ‚   *            )           Ï                     `  â                  >                      >                     >                     >         	  kdisabled       interrupt-controller             Q                     )           Î   >         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie            ñpci                      +            ý    /€       @       	  |pcie-mac            [                     ¢       ÿ      8  �       $       $           ‚       $       $       à          ¬       <              ¶          (  ®      W         X         Q   '         /  pl_250m tl_26m tl_96m tl_32k peri_26m peri_mem          B      H        R              g   9         	  Åpcie-phy            ‚   *           )           Ï                     `  â                  ?                      ?                     ?                     ?         	  kdisabled       interrupt-controller             Q                     )           Î   ?         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor          ý    2À                [      9               ®      o   '      '           spi sf axi                       +            kokay            Çdefault         Õ   @   flash@0           jedec,spi-nor            ý            ðúð€         efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse             ý    Á                              +      usb3-tx-imp@184,1            ý  „                          Î   L      usb3-rx-imp@184,2            ý  „                         Î   K      usb3-intr@185            ý  …                         Î   J      usb3-tx-imp@186,1            ý  †                          Î   I      usb3-rx-imp@186,2            ý  †                         Î   H      usb3-intr@187            ý  ‡                         Î   G      usb2-intr-p0@188,1           ý  ˆ                        usb2-intr-p1@188,2           ý  ˆ                       usb2-intr-p2@189,1           ý  ‰                       usb2-intr-p3@189,2           ý  ‰                       pciephy-rx-ln1@190,1             ý  �                          Î   S      pciephy-tx-ln1-nmos@190,2            ý  �                         Î   R      pciephy-tx-ln1-pmos@191,1            ý  ‘                          Î   Q      pciephy-rx-ln0@191,2             ý  ‘                         Î   P      pciephy-tx-ln0-nmos@192,1            ý  ’                          Î   O      pciephy-tx-ln0-pmos@192,2            ý  ’                         Î   N      pciephy-glb-intr@193             ý  “                          Î   M      dp-data@1ac          ý  ¬           Î   ‰      lvts1-calib@1bc          ý  ¼           Î   /      lvts2-calib@1d0          ý  Ð   8        Î   0      svs-calib@580            ý  €   d        Î   1      socinfo-data1@7a0            ý               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   Ä             kokay       usb-phy@0            ý               ®      ò        ref                    Î   :         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   Å             kokay       usb-phy@0            ý               ®      ô        ref                    Î   ;         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx          ý    È                 ®           Êmipi_tx0_pll            ¡                      	  kdisabled            Î   y      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx          ý    É                 ®           Êmipi_tx1_pll            ¡                      	  kdisabled            Î   z      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    Ð             "€       €        [       š               µ           ®   A          ;      	  main dma                         +          	  kdisabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    Ð            "        €        [       ›               µ           ®   A         ;      	  main dma                         +            kokay            Çdefault         Õ   B        # €      i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    Ð             "€       €        [       œ               µ           ®   A         ;      	  main dma                         +          	  kdisabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s           ý    Ð0                ¡           Î   A      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à             " €       €        [       �               µ           ®   C          ;      	  main dma                         +            kokay            Çdefault         Õ   D        # †       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à            "        €        [       “               µ           ®   C         ;      	  main dma                         +            kokay            Çdefault         Õ   E        # €      i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à             "€       €        [       –               µ           ®   C         ;      	  main dma                         +          	  kdisabled          i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à0            "€       €        [       ˜               µ           ®   C         ;      	  main dma                         +          	  kdisabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c           ý    à@            "        €        [       ™               µ           ®   C         ;      	  main dma                         +            kokay            Çdefault         Õ   F        # €      clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w           ý    àP                ¡           Î   C      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   ã             ‚   *           kokay       usb-phy@0            ý               ®      ð           ref da_ref                     Î   8      usb-phy@700          ý              ®            ð        ref da_ref          ñ   G   H   I        ýintr rx_imp tx_imp                     Î   9         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +                   ä             kokay       usb-phy@0            ý               ®      î           ref da_ref                     Î   5      usb-phy@700          ý              ®            î        ref da_ref          ñ   J   K   L        ýintr rx_imp tx_imp                     Î   6         phy@11e80000              mediatek,mt8195-pcie-phy             ý    è                 |sif         ñ   M   N   O   P   Q   R   S      G  ýglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          ‚   *                     	  kdisabled            Î   =      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy            ý    ú        À         ®            
  unipro mp                     	  kdisabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm            ý             @         ®   T          0  [      �             Œ             ‹               /job mmu gpu            U      (  ‚   *   
   *      *      *      *           &core0 core1 core2 core3 core4         	  kdisabled          clock-controller@13fbf000             mediatek,mt8195-mfgcfg           ý    ûð                ¡           Î   T      syscon@14000000           mediatek,mt8195-vppsys0 syscon           ý                      ¡           9   V                   Î         dma-controller@14001000           mediatek,mt8195-mdp3-rdma            ý                     9   V                  Q              e   W        ‚   *           r   X   €        ®            <  ›   V         V         V         V         V              y         display@14002000              mediatek,mt8195-mdp3-fg          ý                      9   V                   ®             display@14003000              mediatek,mt8195-mdp3-stitch          ý     0                9   V      0            ®            display@14004000              mediatek,mt8195-mdp3-hdr             ý     @                9   V      @            ®      "      display@14005000              mediatek,mt8195-mdp3-aal             ý     P                [      F               9   V      P            ®      
        ‚   *         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý     `                9   V      `            Q    %        ®            display@14007000              mediatek,mt8195-mdp3-tdshp           ý     p                9   V      p            ®      #      display@14008000              mediatek,mt8195-mdp3-color           ý     €                [      I               9   V      €            ®      $        ‚   *         display@14009000              mediatek,mt8195-mdp3-ovl             ý     �                [      J               9   V      �            ®      %        ‚   *           r   X   ‚      display@1400a000              mediatek,mt8195-mdp3-padding             ý                      9   V                   ®              ‚   *         display@1400b000              mediatek,mt8195-mdp3-tcc             ý     °                9   V      °            ®            dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý     À                9   V      À            Q    +        ®              r   X   ƒ        ‚   *           y         mutex@1400f000            mediatek,mt8195-vpp-mutex            ý     ð                [      P               9   V      ð            ®              ‚   *         smi@14010000              mediatek,mt8195-smi-sub-common           ý                     ®                          apb smi gals0           „   Y        ‚   *           Î   Z      smi@14011000              mediatek,mt8195-smi-sub-common           ý                    ®                          apb smi gals0           „   Y        ‚   *           Î   w      smi@14012000              mediatek,mt8195-smi-common-vpp           ý                      ®                                apb smi gals0 gals1         ‚   *           Î   Y      larb@14013000             mediatek,mt8195-smi-larb             ý    0                ‘           „   Z        ®                    apb smi         ‚   *           Î   ]      iommu@14018000            mediatek,mt8195-iommu-vpp            ý    €              8  ¢   [   \   ]   ^   _   `   a   b   c   d   e   f   g   h        [      R               ®              bclk            i           ‚   *           Î   X      clock-controller@14e00000             mediatek,mt8195-wpesys           ý    à                 ¡           Î         clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0          ý    à                 ¡         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1          ý    à0                ¡         larb@14e04000             mediatek,mt8195-smi-larb             ý    à@                ‘           „   i        ®                    apb smi         ‚   *           Î   ~      larb@14e05000             mediatek,mt8195-smi-larb             ý    àP                ‘           „   Y        ®                          apb smi gals            ‚   *           Î   _      syscon@14f00000           mediatek,mt8195-vppsys1 syscon           ý    ð                 ¡           9   V   	               Î         mutex@14f01000            mediatek,mt8195-vpp-mutex            ý    ð                [      {               9   V   	              ®      '        ‚   *         larb@14f02000             mediatek,mt8195-smi-larb             ý    ð                 ‘           „   i        ®                          apb smi gals            ‚   *           Î   }      larb@14f03000             mediatek,mt8195-smi-larb             ý    ð0                ‘           „   Z        ®                          apb smi gals            ‚   *           Î   ^      display@14f06000              mediatek,mt8195-mdp3-split           ý    ð`                9   V   	  `            ®            +      ,        ‚   *         display@14f07000              mediatek,mt8195-mdp3-tcc             ý    ðp                9   V   	  p            ®            dma-controller@14f08000           mediatek,mt8195-mdp3-rdma            ý    ð€                9   V   	  €            Q  „  ¨        ®              r   j            ‚   *           y         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma            ý    ð�                9   V   	  �            Q  …  ©        ®      
        r   j   ¤        ‚   *           y         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma            ý    ð                 9   V   	               Q  †  ª        ®              r   X   À        ‚   *           y         display@14f0b000              mediatek,mt8195-mdp3-fg          ý    ð°                9   V   	  °            ®      	      display@14f0c000              mediatek,mt8195-mdp3-fg          ý    ðÀ                9   V   	  À            ®            display@14f0d000              mediatek,mt8195-mdp3-fg          ý    ðÐ                9   V   	  Ð            ®            display@14f0e000              mediatek,mt8195-mdp3-hdr             ý    ðà                9   V   	  à            ®            display@14f0f000              mediatek,mt8195-mdp3-hdr             ý    ðð                9   V   	  ð            ®            display@14f10000              mediatek,mt8195-mdp3-hdr             ý    ñ                 9   V   
               ®             display@14f11000              mediatek,mt8195-mdp3-aal             ý    ñ                [      i               9   V   
              ®              ‚   *         display@14f12000              mediatek,mt8195-mdp3-aal             ý    ñ                 [      j               9   V   
               ®              ‚   *         display@14f13000              mediatek,mt8195-mdp3-aal             ý    ñ0                [      k               9   V   
  0            ®      !        ‚   *         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý    ñ@                9   V   
  @            Q  �  ¯        ®            display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý    ñP                9   V   
  P            Q  ‘  °        ®      $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz            ý    ñ`                9   V   
  `            Q  ’  ±        ®      %      display@14f17000              mediatek,mt8195-mdp3-tdshp           ý    ñp                9   V   
  p            ®            display@14f18000              mediatek,mt8195-mdp3-tdshp           ý    ñ€                9   V   
  €            ®      (      display@14f19000              mediatek,mt8195-mdp3-tdshp           ý    ñ�                9   V   
  �            ®      )      display@14f1a000              mediatek,mt8195-mdp3-merge           ý    ñ                 9   V   
               ®              ‚   *         display@14f1b000              mediatek,mt8195-mdp3-merge           ý    ñ°                9   V   
  °            ®              ‚   *         display@14f1c000              mediatek,mt8195-mdp3-color           ý    ñÀ                [      t               9   V   
  À            ®              ‚   *         display@14f1d000              mediatek,mt8195-mdp3-color           ý    ñÐ                9   V   
  Ð            [      u               ®              ‚   *         display@14f1e000              mediatek,mt8195-mdp3-color           ý    ñà                [      v               9   V   
  à            ®              ‚   *         display@14f1f000              mediatek,mt8195-mdp3-ovl             ý    ñð                [      w               9   V   
  ð            ®               ‚   *           r   j   ¢      display@14f20000              mediatek,mt8195-mdp3-padding             ý    ò                 9   V                  ®              ‚   *         display@14f21000              mediatek,mt8195-mdp3-padding             ý    ò                9   V                 ®              ‚   *         display@14f22000              mediatek,mt8195-mdp3-padding             ý    ò                 9   V                  ®              ‚   *         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý    ò0                9   V     0            Q  Ÿ  «        ®              r   j   £        ‚   *           y         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý    ò@                9   V     @            Q     ¬        ®              r   j   ¦        ‚   *           y         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot          ý    òP                9   V     P            Q  ¡  ­        ®              r   X   Â        ‚   *           y         clock-controller@15000000             mediatek,mt8195-imgsys           ý                      ¡           Î   $      larb@15001000             mediatek,mt8195-smi-larb             ý                     ‘   	        „   k        ®   $       $       $   
        apb smi gals            ‚   *           Î         smi@15002000              mediatek,mt8195-smi-sub-common           ý                      ®   $      $                 apb smi gals0           „   Y        ‚   *           Î   n      smi@15003000              mediatek,mt8195-smi-sub-common           ý     0                ®   $       $       $   
        apb smi gals0           „   i        ‚   *           Î   k      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top          ý                     ¡           Î   l      larb@15120000             mediatek,mt8195-smi-larb             ý                     ‘   
        „   k        ®   $      l            apb smi         ‚   *           Î   €      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr           ý                     ¡         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe          ý    "                 ¡           Î   m      larb@15230000             mediatek,mt8195-smi-larb             ý    #                 ‘           „   k        ®   $      m            apb smi         ‚   *           Î   �      clock-controller@15330000             mediatek,mt8195-ipesys           ý    3                 ¡           Î   %      larb@15340000             mediatek,mt8195-smi-larb             ý    4                 ‘           „   n        ®   %      %           apb smi         ‚   *           Î   `      clock-controller@16000000             mediatek,mt8195-camsys           ý                      ¡           Î   &      larb@16001000             mediatek,mt8195-smi-larb             ý                     ‘           „   o        ®   &       &       &           apb smi gals            ‚   *           Î   ‚      larb@16002000             mediatek,mt8195-smi-larb             ý                      ‘           „   p        ®   &      &           apb smi         ‚   *           Î   a      smi@16004000              mediatek,mt8195-smi-sub-common           ý     @                ®   &       &       &           apb smi gals0           „   i        ‚   *           Î   o      smi@16005000              mediatek,mt8195-smi-sub-common           ý     P                ®   &      &                 apb smi gals0           „   Y        ‚   *           Î   p      larb@16012000             mediatek,mt8195-smi-larb             ý                     ‘           „   p        ®   q       q            apb smi         ‚   *            Î   b      larb@16013000             mediatek,mt8195-smi-larb             ý    0                ‘           „   o        ®   r       r            apb smi         ‚   *            Î   ƒ      larb@16014000             mediatek,mt8195-smi-larb             ý    @                ‘           „   p        ®   s       s            apb smi         ‚   *   !        Î   h      larb@16015000             mediatek,mt8195-smi-larb             ý    P                ‘           „   o        ®   t       t            apb smi         ‚   *   !        Î   ˆ      clock-controller@1604f000             mediatek,mt8195-camsys_rawa          ý    ð                ¡           Î   q      clock-controller@1606f000             mediatek,mt8195-camsys_yuva          ý    ð                ¡           Î   r      clock-controller@1608f000             mediatek,mt8195-camsys_rawb          ý    ð                ¡           Î   s      clock-controller@160af000             mediatek,mt8195-camsys_yuvb          ý    
ð                ¡           Î   t      clock-controller@16140000             mediatek,mt8195-camsys_mraw          ý                     ¡           Î   u      larb@16141000             mediatek,mt8195-smi-larb             ý                    ‘           „   o        ®   &       u       &           apb smi gals            ‚   *   "        Î   ‡      larb@16142000             mediatek,mt8195-smi-larb             ý                     ‘           „   p        ®   u       u            apb smi         ‚   *   "        Î   g      clock-controller@17200000             mediatek,mt8195-ccusys           ý                      ¡           Î   v      larb@17201000             mediatek,mt8195-smi-larb             ý                     ‘           „   p        ®   v       v            apb smi         ‚   *           Î   c      video-codec@18000000              mediatek,mt8195-vcodec-dec          e   W        r   j                        +             ý                   @                                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc          ý                       r   X  à   X  á         ®      A                  �        sel vdec lat top            B      A        R      �        ‚   *         video-codec@10000             mediatek,mtk-vcodec-lat          ý                      [      Ä             0  r   j      j     j     j     j     j           ®      A                  �        sel vdec lat top            B      A        R      �        ‚   *         video-codec@25000             mediatek,mtk-vcodec-core             ý     P                [      Ã             P  r   j      j  ¡   j  ¢   j  £   j  ¤   j  ¥   j  ¦   j  §   j  ¨   j  ©         ®      A                  �        sel vdec lat top            B      A        R      �        ‚   *            larb@1800d000             mediatek,mt8195-smi-larb             ý     Ð                ‘           „   i        ®                      apb smi         ‚   *           Î   †      larb@1800e000             mediatek,mt8195-smi-larb             ý     à                ‘           „   w        ®                     apb smi         ‚   *           Î   f      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc          ý     ð                ¡           Î         larb@1802e000             mediatek,mt8195-smi-larb             ý    à                ‘           „   i        ®                      apb smi         ‚   *           Î   …      clock-controller@1802f000             mediatek,mt8195-vdecsys          ý    ð                ¡           Î         larb@1803e000             mediatek,mt8195-smi-larb             ý    à                ‘           „   w        ®                      apb smi         ‚   *           Î   e      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1            ý    ð                ¡           Î          clock-controller@190f3000             mediatek,mt8195-apusys_pll           ý    0                ¡         clock-controller@1a000000             mediatek,mt8195-vencsys          ý                      ¡           Î   !      larb@1a010000             mediatek,mt8195-smi-larb             ý                     ‘           „   i        ®   !      !           apb smi         ‚   *           Î   „      video-codec@1a020000              mediatek,mt8195-vcodec-enc           ý                   H  r   j  `   j  a   j  b   j  c   j  d   j  v   j  w   j  x   j  y        [      U               e   W        ®   !         	  venc_sel            B      @        R      �        ‚   *                        +         jpgdec-master             mediatek,mt8195-jpgdec          ‚   *         0  r   j  m   j  n   j  r   j  s   j  t   j  u                     +               jpgdec@1a040000           mediatek,mt8195-jpgdec-hw            ý                   0  r   j  m   j  n   j  r   j  s   j  t   j  u        [      W               ®   !           jpgdec          ‚   *         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw            ý                   0  r   j  m   j  n   j  r   j  s   j  t   j  u        [      X               ®   !           jpgdec          ‚   *         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw            ý                   0  r   X  �   X  Ž   X  ’   X  “   X  ”   X  •        [      \               ®   "           jpgdec          ‚   *            clock-controller@1b000000             mediatek,mt8195-vencsys_core1            ý                      ¡           Î   "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon             ý                     ›   x               ¡           9   x                  Î         jpgenc-master             mediatek,mt8195-jpgenc          ‚   *            r   X  ‡   X  ˆ   X  ‰   X  Œ                     +               jpgenc@1a030000           mediatek,mt8195-jpgenc-hw            ý                      r   j  g   j  h   j  i   j  l        [      V               ®   !           jpgenc          ‚   *         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw            ý                      r   X  ‡   X  ˆ   X  ‰   X  Œ        [      [               ®   "           jpgenc          ‚   *            larb@1b010000             mediatek,mt8195-smi-larb             ý                     ‘           „   Y        ®   "      "                  apb smi gals            ‚   *           Î   d      ovl@1c000000              mediatek,mt8195-disp-ovl             ý                      [      |               ‚   *           ®               r   j           9   x                rdma@1c002000             mediatek,mt8195-disp-rdma            ý                      [      ~               ‚   *           ®              r   j            9   x                color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color            ý     0                [                     ‚   *           ®              9   x     0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr            ý     @                [      €               ‚   *           ®              9   x     @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal            ý     P                [      �               ‚   *           ®              9   x     P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma            ý     `                [      ‚               ‚   *           ®              9   x     `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither          ý     p                [      ƒ               ‚   *           ®      	        9   x     p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi          ý     €                [      „               ‚   *           ®            *   y        engine digital hs           g   y        Ådphy          	  kdisabled          dsc@1c009000              mediatek,mt8195-disp-dsc             ý     �                [      …               ‚   *           ®              9   x     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi          ý                     [      Ž               ‚   *           ®            +   z        engine digital hs           g   z        Ådphy          	  kdisabled          merge@1c014000            mediatek,mt8195-disp-merge           ý    @                [      �               ‚   *           ®              9   x     @          dp-intf@1c015000              mediatek,mt8195-dp-intf          ý    P                [      ‘               ®      ,                    pixel engine pll          	  kdisabled          mutex@1c016000            mediatek,mt8195-disp-mutex           ý    `                [      ’               ‚   *           ®              9   x     `            Q  U      larb@1c018000             mediatek,mt8195-smi-larb             ý    €                ‘            „   i        ®      (      (              apb smi gals            ‚   *           Î   {      larb@1c019000             mediatek,mt8195-smi-larb             ý    �                ‘           „   Y        ®      (                     apb smi gals            ‚   *           Î   [      syscon@1c100000           mediatek,mt8195-vdosys1 syscon           ý                     ›   x              9   x                  ¡           o           Î   #      smi@1c01b000              mediatek,mt8195-smi-common-vdo           ý    °                 ®      %      &      )      $        apb smi gals0 gals1         ‚   *           Î   i      iommu@1c01f000            mediatek,mt8195-iommu-vdo            ý    ð              8  ¢   {   |   }   ~      €   �   ‚   ƒ   „   …   †   ‡   ˆ        [      �               i           ®      '        bclk            ‚   *           Î   j      mutex@1c101000            mediatek,mt8195-disp-mutex           ý                    [      î               ‚   *           ®   #           9   x                 Q  À      larb@1c102000             mediatek,mt8195-smi-larb             ý                     ‘           „   i        ®   #       #       #           apb smi gals            ‚   *           Î   |      larb@1c103000             mediatek,mt8195-smi-larb             ý    0                ‘           „   Y        ®   #      #                  apb smi gals            ‚   *           Î   \      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma            ý    @                [      ï               ®   #           ‚   *           r   j   @        9   x     @            y         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma            ý    P                [      ð               ®   #           ‚   *           r   X   `        9   x     P            y         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma            ý    `                [      ñ               ®   #           ‚   *           r   j   A        9   x     `            y         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma            ý    p                [      ò               ®   #           ‚   *           r   X   a        9   x     p            y         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma            ý    €                [      ó               ®   #           ‚   *           r   j   B        9   x     €            y         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma            ý    �                [      ô               ®   #           ‚   *           r   X   b        9   x     �            y         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma            ý                     [      õ               ®   #           ‚   *           r   j   C        9   x                  y         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma            ý    °                [      ö               ®   #           ‚   *           r   X   c        9   x     °            y         vpp-merge@1c10c000            mediatek,mt8195-disp-merge           ý    À                [      ÷               ®   #   	   #           merge merge_async           ‚   *           9   x     À             ±        ´   #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge           ý    Ð                [      ø               ®   #   
   #           merge merge_async           ‚   *           9   x     Ð             ±        ´   #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge           ý    à                [      ù               ®   #      #           merge merge_async           ‚   *           9   x     à             ±        ´   #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge           ý    ð                [      ú               ®   #      #           merge merge_async           ‚   *           9   x     ð             ±        ´   #         vpp-merge@1c110000            mediatek,mt8195-disp-merge           ý                     [      û               ®   #      #           merge merge_async           ‚   *           9   x                   Å        ´   #         dp-intf@1c113000              mediatek,mt8195-dp-intf          ý    0                [                     ‚   *           ®   #   /   #                 pixel engine pll          	  kdisabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p   ý    @            P            p            �                         °            À              4  |mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  9   x     @       x     P       x     p       x     �       x             x     °       x     À          h  ®   #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *            ƒ  mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          ‚   *           r   X   d   X   e        [                   (  ´   #   3   #   4   #   5   #   6   #   7      E  »vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx           ý    P        €         ñ   ‰        ýdp_calibration_data         ‚   *           [      ¤               Ü  ¤      	  kdisabled          dp-tx@1c600000            mediatek,mt8195-dp-tx            ý    `        €         ñ   ‰        ýdp_calibration_data         ‚   *           [      Ê               Ü  ¤      	  kdisabled             thermal-zones      cpu0-thermal            í  è        û   ú           Š      trips      trip-alert          ! L        -  Ð         øpassive         Î   ‹      trip-crit           ! †         -  Ð      	   øcritical             cooling-maps       map0            8   ‹      0  =   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            í  è        û   ú           Š      trips      trip-alert          ! L        -  Ð         øpassive         Î   Œ      trip-crit           ! †         -  Ð      	   øcritical             cooling-maps       map0            8   Œ      0  =   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            í  è        û   ú           Š      trips      trip-alert          ! L        -  Ð         øpassive         Î   �      trip-crit           ! †         -  Ð      	   øcritical             cooling-maps       map0            8   �      0  =   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            í  è        û   ú           Š      trips      trip-alert          ! L        -  Ð         øpassive         Î   Ž      trip-crit           ! †         -  Ð      	   øcritical             cooling-maps       map0            8   Ž      0  =   	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            í  è        û   ú           Š       trips      trip-alert          ! L        -  Ð         øpassive         Î   �      trip-crit           ! †         -  Ð      	   øcritical             cooling-maps       map0            8   �      0  =   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            í  è        û   ú           Š      trips      trip-alert          ! L        -  Ð         øpassive         Î   �      trip-crit           ! †         -  Ð      	   øcritical             cooling-maps       map0            8   �      0  =   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            í  è        û   ú           Š      trips      trip-alert          ! L        -  Ð         øpassive         Î   ‘      trip-crit           ! †         -  Ð      	   øcritical             cooling-maps       map0            8   ‘      0  =   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            í  è        û   ú           Š      trips      trip-alert          ! L        -  Ð         øpassive         Î   ’      trip-crit           ! †         -  Ð      	   øcritical             cooling-maps       map0            8   ’      0  =   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            í  è        û   ú           “      trips      trip-alert          ! L        -  Ð         øpassive       trip-crit           ! †         -  Ð      	   øcritical                vpu1-thermal            í  è        û   ú           “   	   trips      trip-alert          ! L        -  Ð         øpassive       trip-crit           ! †         -  Ð      	   øcritical                gpu-thermal         í  è        û   ú           “   
   trips      trip-alert          ! L        -  Ð         øpassive       trip-crit           ! †         -  Ð      	   øcritical                gpu1-thermal            í  è        û   ú           “      trips      trip-alert          ! L        -  Ð         øpassive       trip-crit           ! †         -  Ð      	   øcritical                vdec-thermal            í  è        û   ú           “      trips      trip-alert          ! L        -  Ð         øpassive       trip-crit           ! †         -  Ð      	   øcritical                img-thermal         í  è        û   ú           “      trips      trip-alert          ! L        -  Ð         øpassive       trip-crit           ! †         -  Ð      	   øcritical                infra-thermal           í  è        û   ú           “      trips      trip-alert          ! L        -  Ð         øpassive       trip-crit           ! †         -  Ð      	   øcritical                cam0-thermal            í  è        û   ú           “      trips      trip-alert          ! L        -  Ð         øpassive       trip-crit           ! †         -  Ð      	   øcritical                cam1-thermal            í  è        û   ú           “      trips      trip-alert          ! L        -  Ð         øpassive       trip-crit           ! †         -  Ð      	   øcritical                   chosen          Lserial0:921600n8          memory@40000000          ñmemory           ý    @       €            	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 serial0 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux bias-pull-up drive-strength drive-strength-microamp bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents #iommu-cells #mbox-cells power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 #io-channel-cells nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup usb2-lpm-disable bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-max-frequency bits #phy-cells operating-points-v2 power-domain-names mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path 