Ðþí [È   8 P   (            Ä OÌ                             6    kontron,3-5-sbc-i1200 mediatek,mt8395 mediatek,mt8195                                    +            7Kontron 3.5"-SBC-i1200     aliases          =/soc/dp-intf@1c015000            F/soc/dp-intf@1c113000            O/soc/mailbox@10320000            T/soc/mailbox@10330000            Y/soc/hdr-engine@1c114000             `/soc/mutex@1c016000          g/soc/mutex@1c101000          n/soc/vpp-merge@1c10c000          u/soc/vpp-merge@1c10d000          |/soc/vpp-merge@1c10e000          ƒ/soc/vpp-merge@1c10f000          Š/soc/vpp-merge@1c110000          ‘/soc/dma-controller@1c104000             œ/soc/dma-controller@1c105000             §/soc/dma-controller@1c106000             ²/soc/dma-controller@1c107000             ½/soc/dma-controller@1c108000             È/soc/dma-controller@1c109000             Ó/soc/dma-controller@1c10a000             Þ/soc/dma-controller@1c10b000             é/soc/mmc@11230000            î/soc/mmc@11240000            ó/soc/serial@11001200             û/soc/serial@11001300            /soc/serial@11001400            /soc/serial@11001500            /soc/serial@11001100          cpus                         +       cpu@0           cpu           arm,cortex-a55          '            +psci            9               Mec3@        ]  4        p              €  €         �   @        Ÿ   €        ¬  €         ¹   @        Ë   €        Ø           é           ø   	      cpu@100         cpu           arm,cortex-a55          '           +psci            9               Mec3@        ]  4        p              €  €         �   @        Ÿ   €        ¬  €         ¹   @        Ë   €        Ø           é           ø   
      cpu@200         cpu           arm,cortex-a55          '           +psci            9               Mec3@        ]  4        p              €  €         �   @        Ÿ   €        ¬  €         ¹   @        Ë   €        Ø           é           ø         cpu@300         cpu           arm,cortex-a55          '           +psci            9               Mec3@        ]  4        p              €  €         �   @        Ÿ   €        ¬  €         ¹   @        Ë   €        Ø           é           ø         cpu@400         cpu           arm,cortex-a78          '           +psci            9              M�fÔÀ        ]           p              €           �   @        Ÿ           ¬           ¹   @        Ë           Ø           é           ø         cpu@500         cpu           arm,cortex-a78          '           +psci            9              M�fÔÀ        ]           p              €           �   @        Ÿ           ¬           ¹   @        Ë           Ø           é           ø         cpu@600         cpu           arm,cortex-a78          '           +psci            9              M�fÔÀ        ]           p              €           �   @        Ÿ           ¬           ¹   @        Ë           Ø           é           ø         cpu@700         cpu           arm,cortex-a78          '           +psci            9              M�fÔÀ        ]           p              €           �   @        Ÿ           ¬           ¹   @        Ë           Ø           é           ø         cpu-map    cluster0       core0               	      core1               
      core2                     core3                     core4                     core5                     core6                     core7                           idle-states         psci       cpu-retention-l           arm,idle-state                     (        9   2        J   _        Z  D        ø         cpu-retention-b           arm,idle-state                     (        9   -        J   Œ        Z  ä        ø         cpu-off-l             arm,idle-state                    (        9   7        J   ›        Z  H        ø         cpu-off-b             arm,idle-state                    (        9   2        J   È        Z  è        ø            l2-cache0             cache           k           ‚           �   @        ¡           Ø            w        ø         l2-cache1             cache           k           ‚           �   @        ¡           Ø            w        ø         l3-cache              cache           k           ‚            �   @        ¡            w        ø            dsu-pmu           arm,dsu-pmu         …                       �   	   
                          •fail          dmic-codec            dmic-codec          œ           ©   2      mt8195-sound            ¹         	  •disabled          fixed-factor-clock-13m            fixed-factor-clock          Ë            Ø           ß           é           ôclk13m          ø   (      oscillator-26m            fixed-clock         Ë            MŒº€        ôclk26m          ø         oscillator-32k            fixed-clock         Ë            M  €         ôclk32k        performance-controller@11bc10             mediatek,cpufreq-hw          '     ¼            ½0                          ø         opp-table-gpu             operating-points-v2          !        ø   m   opp-390000000           ,    >í€        3 	‰h      opp-410000000           ,    p€        3 	¡Ò      opp-431000000           ,    °‰À        3 	¡Ò      opp-473000000           ,    1h@        3 	º<      opp-515000000           ,    ²FÀ        3 	º<      opp-556000000           ,    !#ã         3 	Ò¦      opp-598000000           ,    #¤Á€        3 	ë      opp-640000000           ,    &%          3 	ë      opp-670000000           ,    'ïc€        3 
ä      opp-700000000           ,    )¹'         3 
L¸      opp-730000000           ,    +‚ê€        3 
}Œ      opp-760000000           ,    -L®         3 
®`      opp-790000000           ,    /q€        3 
ß4      opp-820000000           ,    0à5         3       opp-850000000           ,    2©ø€        3 @Ü      opp-880000000           ,    4s¼         3 q°         pmu-a55           arm,cortex-a55-pmu                      …                  pmu-a78           arm,cortex-a78-pmu                      …                  psci              arm,psci-1.0            2smc       timer             arm,armv8-timer                   @  …                                             
             soc                      +             simple-bus           A        H                          interrupt-controller@c000000              arm,gic-v3          S           d                        {         '                                    …      	               ø      ppi-partitions     interrupt-partition-0           �   	   
              ø         interrupt-partition-1           �                    ø               syscon@10000000            mediatek,mt8195-topckgen syscon         '                      Ë           ø         syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          '                     Ë           ™           ø         syscon@10003000           mediatek,mt8195-pericfg syscon          '     0                Ë           ø   A      pinctrl@10005000              mediatek,mt8195-pinctrl       €  '     P            Ñ             Ó             Ô             â             ë             ô              °              B  ¦iocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            °        À           Ì              �         {        …       ë               S           ø      eth-default-pins            ø   =   pins-txd            Ø  M  N  O  P        ß         pins-rxd            Ø  Q  R  S  T      pins-cc         Ø  U  V  W  X        ß         pins-mdio           Ø  Y  Z         î      pins-power          Ø  [   \          û      pins-reset          Ø  ]          û      pins-interrupt          Ø  ^          î         eth-sleep-pins          ø   >   pins-txd            Ø  M   N   O   P       pins-cc         Ø  U   X   W   V       pins-rxd            Ø  Q   R   S   T       pins-mdio           Ø  Y   Z                            gpio-keys-pins          ø   °   pins            Ø  j          î         i2c0-pins           ø   Z   pins            Ø    	        "   Ï        /  è         i2c1-pins           ø   [   pins            Ø  
          "   Ï        /  è         i2c2-default-pins           ø   \   pins-bus            Ø            "   Ï        /  è         i2c3-pins           ø   ]   pins            Ø            "   Ï        /  è         i2c4-pins           ø   ^   pins            Ø            "   Ï        /  è         i2c6-pins           ø   W   pins            Ø             "        /  è         mmc0-default-pins           ø   C   pins-clk            Ø  z        ß           G   f      pins-cmd-dat          $  Ø  ~  }  |  {  w  v  u  t  y         î        ß           "   e      pins-rst            Ø  x        ß           "   e         mmc0-uhs-pins           ø   D   pins-clk            Ø  z        ß           G   f      pins-cmd-dat          $  Ø  ~  }  |  {  w  v  u  t  y         î        ß           "   e      pins-ds         Ø          ß           G   f      pins-rst            Ø  x        ß           "   e         mmc1-default-pins           ø   G   pins-clk            Ø  o        ß           G   f      pins-cmd-dat            Ø  n  p  q  r  s         î        ß           "   e         mmc1-detect-pins            ø   H   pins-insert         Ø  �          "         nor-default-pins            ø   U   pins-ck-io          Ø  Ž  �  �        ß            G      pins-cs         Ø  Œ        ß            "         pcie0-default-pins          ø   Q   pins-bus            Ø               "         pcie1-default-pins          ø   T   pins-bus            Ø               "   e         led-pins            ø   ±   pins-power-en           Ø  k          û         spi0-default-pins           ø   4   pins-cs-mosi-clk            Ø  „  †  …               pins-miso           Ø  ‡         G         spi1-default-pins           ø   8   pins-cs-mosi-clk            Ø  ˆ  Š  ‰               pins-miso           Ø  ‹         G         uart0-pins          ø   /   pins-rx         Ø  c         î         "      pins-tx         Ø  b         uart1-pins          ø   0   pins-rx         Ø  g         î         "      pins-tx         Ø  f      pins-rts            Ø  d      pins-cts            Ø  e         î         uart2-pins          ø   1   pins-rx         Ø  D         î         "      pins-tx         Ø  C      pins-rts            Ø  B      pins-cts            Ø  A         î         uart3-pins          ø   2   pins-rx         Ø           î        "   e      pins-tx         Ø           uart4-pins          ø   3   pins-rx         Ø           î         "      pins-tx         Ø              syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            '     `           power-controller          !    mediatek,mt8195-power-controller                         +            V           ø   +   power-domain@8          '                        +            V      power-domain@9          '   	        Ø                    jmfg alt         v                        +            V      power-domain@10         '   
        V          power-domain@11         '           V          power-domain@12         '           V          power-domain@13         '           V          power-domain@14         '           V                power-domain@15         '         Ø  Ø                        	      @      A      K      à                                                                                                                          jvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           v                        +            V      power-domain@16         '         8  Ø      â      $      %      &      '      (      )      D  jvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         v                        +            V      power-domain@17         '           Ø      á                    jvppsys1 vppsys1-0 vppsys1-1         v           V          power-domain@22         '            Ø                              $  jwepsys-0 wepsys-1 wepsys-2 wepsys-3         v           V          power-domain@23         '           Ø               jvdec0-0         v                        +            V       power-domain@24         '           Ø               jvdec1-0         v           V          power-domain@25         '           Ø                jvdec2-0         v           V             power-domain@26         '           Ø   !            jvenc0-larb          v                        +            V       power-domain@27         '           Ø   "            jvenc1-larb          v           V             power-domain@18         '            Ø      ã   #       #      #         &  jvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           v                        +            V      power-domain@19         '           v           V          power-domain@20         '           v           V          power-domain@21         '           Ø      Q        jhdmi_tx         V             power-domain@28         '           Ø   $       $   
        jimg-0 img-1         v                        +            V      power-domain@29         '           V          power-domain@30         '           Ø         $      %           jipe ipe-0 ipe-1         v           V             power-domain@31         '         (  Ø   &       &      &      &      &           jcam-0 cam-1 cam-2 cam-3 cam-4           v                        +            V      power-domain@32         '            V          power-domain@33         '   !        V          power-domain@34         '   "        V                   power-domain@0          '            v           V          power-domain@1          '           v           V          power-domain@2          '           V          power-domain@3          '           V          power-domain@4          '           Ø      5      7        jcsi_rx_top csi_rx_top1          V          power-domain@5          '           Ø   '           jether           V          power-domain@6          '           Ø      X      n        jadsp adsp1                       +            v           V      power-domain@7          '            Ø      g      "      n      2        jaudio audio1 audio2 audio3          v           V                   watchdog@10007000             mediatek,mt8195-wdt          ˆ        '     p                ™           ø   .      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           '     À                Ë           ø         timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         '    p                …      	               Ø   (      pwrap@10024000            mediatek,mt8195-pwrap syscon            '    @                ¦pwrap           …       ó               Ø                   	  jspi wrap                   $        °      Ë   pmic              mediatek,mt6359          {        S           Ç      Þ      adc           mediatek,mt6359-auxadc          Û         mt6359codec       regulators            mediatek,mt6359-regulator      buck_vs1            ívs1         ü 5          !‘À        ,             H      buck_vgpu11         ívgpu11          ü €         7        \  ˆ        ,   È        q                   H      buck_vmodem         ívmodem          ü €         Èà        \  *        ,   È      buck_vpu            ívpu         ü €         7        \  ˆ        ,   È        q                   H      buck_vcore          ívcore           ü €         Ö         \  ˆ        ,   È        q                   H      buck_vs2            ívs2         ü 5          j         ,             H      buck_vpa            ívpa         ü ¡          7±Ð        ,  ,      buck_vproc2         ívproc2          ü €         7        \  L        ,   È        q                   H      buck_vproc1         ívproc1          ü €         7        \  L        ,   È        q                   H      buck_vcore_sshub            ívcore_sshub         ü €         7      buck_vgpu11_sshub           ívgpu11_sshub            ü €         7      ldo_vaud18          ívaud18          ü w@         w@        ,   ð      ldo_vsim1           ívsim1           ü ð          /M`      ldo_vibr            ívibr            ü O€         2Z       ldo_vrf12           ívrf12           ü Èà         Ö          H      ldo_vusb            ívusb            ü -ÆÀ         -ÆÀ        ,  À         H        ø   B      ldo_vsram_proc2         ívsram_proc2         ü ¡          ½¶        \  L        ,   ð         H      ldo_vio18           ívio18           ü ð          ýà        ,  À         H      ldo_vcamio          ívcamio          ü ð          ýà      ldo_vcn18           ívcn18           ü w@         w@        ,   ð      ldo_vfe28           ívfe28           ü *¹€         *¹€        ,   x      ldo_vcn13           ívcn13           ü »          Ö       ldo_vcn33_1_bt          ívcn33_1_bt          ü *¹€         5gà      ldo_vcn33_1_wifi            ívcn33_1_wifi            ü *¹€         5gà      ldo_vaux18          ívaux18          ü w@         w@        ,   ð         H      ldo_vsram_others            ívsram_others            ü ¡          ½¶        \  ˆ        ,   ð         H      ldo_vefuse          ívefuse          ü ð          „€      ldo_vxo22           ívxo22           ü w@         !‘À         H      ldo_vrfck           ívrfck           ü ã`         ð       ldo_vrfck_1         ívrfck           ü ëÀ         j       ldo_vbif28          ívbif28          ü *¹€         *¹€        ,   ð      ldo_vio28           ívio28           ü *¹€         2Z          H      ldo_vemc            ívemc            ü ,@          2Z       ldo_vemc_1          ívemc            ü &%          2Z         ø   E      ldo_vcn33_2_bt          ívcn33_2_bt          ü *¹€         5gà      ldo_vcn33_2_wifi            ívcn33_2_wifi            ü *¹€         5gà      ldo_va12            íva12            ü O€         Ö          H      ldo_va09            íva09            ü 5          O€      ldo_vrf18           ívrf18           ü ð          žP      ldo_vsram_md          	  ívsram_md            ü ¡          ½¶        \  *        ,   ð         H      ldo_vufs            ívufs            ü ð          ýà        ø   F      ldo_vm18            ívm18            ü ð          ýà         H      ldo_vbbck           ívbbck           ü Èà         O€         H      ldo_vsram_proc1         ívsram_proc1         ü ¡          ½¶        \  L        ,   ð         H      ldo_vsim2           ívsim2           ü ð          /M`      ldo_vsram_others_sshub          ívsram_others_sshub          ü ¡          ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             '    p            �                ¦pmif spmimst            Ø                   E      (  jpmif_sys_ck pmif_tmr_ck spmimst_clk_mux                $        °      Ë                     +       mt6315@6              mediatek,mt6315-regulator           '          regulators     vbuck1          íVbcpu           ü “à         7        ,           \  j        q                   H            mt6315@7              mediatek,mt6315-regulator           '          regulators     vbuck1          íVgpu            ü 	‰h         7        ,           \  j        q                   H        ø   n               infra-iommu@10315000              mediatek,mt8195-iommu-infra         '    1P       P       P  …                                                                         ‰           ø   N      mailbox@10320000              mediatek,mt8195-gce         '    2        @         …       â               –           Ø              ø   ‘      mailbox@10330000              mediatek,mt8195-gce         '    3        @         …       ä               –           Ø              ø   o      scp@10500000              mediatek,mt8195-scp       0  '    P             r             p        €         ¦sram cfg l1tcm          …      Î               •okay            ¢   )        °mediatek/mt8195/scp.img         ø   p      clock-controller@10720000             mediatek,mt8195-scp_adsp            '    r                 Ë           ø   *      dsp@10803000              mediatek,mt8195-dsp          '    €0            „               	  ¦cfg sram          ,  Ø      X         n      Š   *          #      K  jadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h          ¾   +           Ìrx tx           ×   ,   -      	  •disabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           –            '    �`                …      ¾               ø   ,      mailbox@10817000              mediatek,mt8195-adsp-mbox           –            '    �p                …      ¿               ø   -      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           '    ‰                 Þ           ¾   +           …      6               ð   .         	  ÷audiosys          ”  Ø                     Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d      2   *          ó  jclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  •disabled            ø         serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …       �               Ø               	  jbaud bus            •okay            default            /      serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …       Ž               Ø               	  jbaud bus            •okay            default            0               serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …       �               Ø               	  jbaud bus            •okay            default            1               serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …      Ó               Ø               	  jbaud bus            •okay            default            2      serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …      Ô               Ø               	  jbaud bus            •okay            default            3      serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           '                     …      Õ               Ø               	  jbaud bus          	  •disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           '                      Ø              jmain            Û           •okay            ø   ²      syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           '     0                Ë           ø   '      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '                      …       ¿               Ø      ™                    jparent-clk sel-clk spi-clk          •okay            default            4        +       tpm@0         !    infineon,slb9670 tcg,tpm_tis-spi            '            ?I          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         '     °                …       ©               Ø              ð               Q   5   6      $  ]lvts-calib-data-1 lvts-calib-data-2         n           ø   ¬      svs@1100bc00              mediatek,mt8195-svs         '     ¼                …       Ç               Ø              jmain            Q   7   5      (  ]svs-calibration-data t-calibration-data         ð              ÷svs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           '     à                …       Ë               ¾   +           „           Ø      *      0        jmain mm       	  •disabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           '     ð                …                     „           Ø      +      N        jmain mm       	  •disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '                     …       À               Ø      ™            3        jparent-clk sel-clk spi-clk          •okay            default            8        +          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '                     …       Á               Ø      ™            4        jparent-clk sel-clk spi-clk        	  •disabled          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '    0                …       Â               Ø      ™            5        jparent-clk sel-clk spi-clk        	  •disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '    €                …       Ã               Ø      ™            <        jparent-clk sel-clk spi-clk        	  •disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            '    �                …       Ä               Ø      ™            =        jparent-clk sel-clk spi-clk        	  •disabled          spi@1101d000              mediatek,mt8195-spi-slave           '    Ð                …       Å               Ø      R        jspi                        °      ˜      	  •disabled          spi@1101e000              mediatek,mt8195-spi-slave           '    à                …       Æ               Ø      S        jspi                        °      ˜      	  •disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           '           @         …      Ì               �macirq        .  jaxi apb mac_main ptp_ref rmii_internal mac_cg         0  Ø   '       '         R      S      T   '                  R      S      T        °      Â      Ã      Ä        ¾   +           Ÿ           °   9        À   :        Ó   ;        æ           ñ           ü            •okay          	  	rgmii-id               <        default sleep              =           >   mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916            '           Ç      ^           '  '        7 8€        I      ]            ø   <         stmmac-axi-config           U           e           u                                 ø   9      rx-queues-config                        •        ø   :   queue0           ¦        ¹          queue1           ¦        ¹          queue2           ¦        ¹          queue3           ¦        ¹             tx-queues-config            Ñ            ç        ø   ;   queue0          ù            ¦                  queue1          ù            ¦                 queue2          ù            ¦                 queue3          ù            ¦                       usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           '            -ÿ     >              	  ¦mac ippc            A                     ?                      +           …       €               Ø      /      í      B        jsys_ck ref_ck mcu_ck               ?      @                    &   A      g        •okay            =host            E   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          '                       ¦mac         …       �                      ,      -        °      –      –      $  Ø      /      í               B      $  jsys_ck ref_ck mcu_ck dma_ck xhci_ck         •okay             mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          '    #             õ                 …       ƒ               Ø                          jsource hclk source_cg           •okay            default state_uhs              C           D        S           CëÂ         ] L         l         ~         �         ž         ­         µ         »        É   E        Õ   F      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          '    $             Ç                 …       ‡               Ø                  $        jsource hclk source_cg                          °      ¿        •okay            default state_uhs              G   H           G        â      �           S           CëÂ          ë         ü         		         	        É   I        Õ   J      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          '    %             æ                 …       ˆ               Ø                   I        jsource hclk source_cg                           °      ¿      	  •disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            '    '€                …       ª               Ø              ð              Q   5   6      $  ]lvts-calib-data-1 lvts-calib-data-2         n           ø   £      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           '    )             )>              	  ¦mac ippc            …                        K                  .      /        °      –      –      $  Ø   '         ï            '         $  jsys_ck ref_ck mcu_ck dma_ck xhci_ck         &   A      h                 •okay            E   B        	         usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           '    *       -ÿ    *>              	  ¦mac ippc            A            *        ?                      +           …                            0        °      –        Ø   '         ñ   '           jsys_ck ref_ck mcu_ck               L                    &   A      i        •okay            E   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          '                       ¦mac         …                            1        °      –        Ø   '           jsys_ck          •okay             usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           '    +       -ÿ    +>              	  ¦mac ippc            A            +        ?                      +           …                            2        °      –        Ø   '         ó   '   	        jsys_ck ref_ck mcu_ck               M                    &   A      j        •okay            E   B   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          '                       ¦mac         …                            3        °      –        Ø   '   	        jsys_ck          •okay             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +           '    /        @       	  ¦pcie-mac            …                     	3       ÿ      8  A�                           ‚                       à          	=       N              	G          0  Ø      V      #      &      +      K   '         /  jpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                 G        °                 O      	  	Vpcie-phy            ¾   +            S           	`                     `  	s                  P                      P                     P                     P           •okay            default            Q   interrupt-controller             {                     S           ø   P         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           pci                      +           '    /€       @       	  ¦pcie-mac            …                     	3       ÿ      8  A�       $       $           ‚       $       $       à          	=       N              	G          (  Ø      W         X         Q   '         /  jpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                 H        °                 R         	  	Vpcie-phy            ¾   +           S           	`                     `  	s                  S                      S                     S                     S           •okay            default            T   interrupt-controller             {                     S           ø   S         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         '    2À                …      9               Ø      o   '      '           jspi sf axi                       +            •okay            default            U   flash@0           jedec,spi-nor           '            ?u         	�           	’            efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            '    Á                              +      usb3-tx-imp@184,1           '  „           	£               ø   d      usb3-rx-imp@184,2           '  „           	£              ø   c      usb3-intr@185           '  …           	£              ø   b      usb3-tx-imp@186,1           '  †           	£               ø   a      usb3-rx-imp@186,2           '  †           	£              ø   `      usb3-intr@187           '  ‡           	£              ø   _      usb2-intr-p0@188,1          '  ˆ           	£             usb2-intr-p1@188,2          '  ˆ           	£            usb2-intr-p2@189,1          '  ‰           	£            usb2-intr-p3@189,2          '  ‰           	£            pciephy-rx-ln1@190,1            '  �           	£               ø   k      pciephy-tx-ln1-nmos@190,2           '  �           	£              ø   j      pciephy-tx-ln1-pmos@191,1           '  ‘           	£               ø   i      pciephy-rx-ln0@191,2            '  ‘           	£              ø   h      pciephy-tx-ln0-nmos@192,1           '  ’           	£               ø   g      pciephy-tx-ln0-pmos@192,2           '  ’           	£              ø   f      pciephy-glb-intr@193            '  “           	£               ø   e      dp-data@1ac         '  ¬           ø   ¢      lvts1-calib@1bc         '  ¼           ø   5      lvts2-calib@1d0         '  Ð   8        ø   6      svs-calib@580           '  €   d        ø   7      socinfo-data1@7a0           '               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A        Ä             •okay       usb-phy@0           '               Ø      ò        jref         	¨           ø   L         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A        Å             •okay       usb-phy@0           '               Ø      ô        jref         	¨           ø   M         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         '    È                 Ø           ômipi_tx0_pll            Ë            	¨          	  •disabled            ø   ’      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         '    É                 Ø           ômipi_tx1_pll            Ë            	¨          	  •disabled            ø   “      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    Ð             "€       €        …       š               ß           Ø   V          ;      	  jmain dma                         +          	  •disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    Ð            "        €        …       ›               ß           Ø   V         ;      	  jmain dma                         +            •okay            M €           W        default    pmic@34           mediatek,mt6360         '   4         {        Ç      e           �IRQB            S      regulator             mediatek,mt6360-regulator           	³   X        	Ã   X        	Ó   X   buck1         	  íemi_vdd2            ü 	'À         w@        q                   H      buck2         	  íemi_vddq            ü “à         Ö         q                   H      ldo1            ímt6360_ldo1         ü O€         6î€        q             ldo2            ípanel1_p1v8         ü w@         w@        q             ldo3            ívmc_pmu         ü w@         2Z         q               ø   J      ldo5          	  ívmch_pmu            ü 2Z          2Z         q               ø   I      ldo6            ímt6360_ldo6         ü ¡                    q             ldo7            íemi_vmddr_en            ü w@         w@        q                H               i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    Ð             "€       €        …       œ               ß           Ø   V         ;      	  jmain dma                         +          	  •disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          '    Ð0                Ë           ø   V      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    à             " €       €        …       �               ß           Ø   Y          ;      	  jmain dma                         +            •okay            default            Z        M †       i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    à            "        €        …       “               ß           Ø   Y         ;      	  jmain dma                         +            •okay            default            [        M †       i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    à             "€       €        …       –               ß           Ø   Y         ;      	  jmain dma                         +            •okay            default            \        M €      i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    à0            "€       €        …       ˜               ß           Ø   Y         ;      	  jmain dma                         +            •okay            default            ]        M †       i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          '    à@            "        €        …       ™               ß           Ø   Y         ;      	  jmain dma                         +            •okay            M †            ^        default       clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          '    àP                Ë           ø   Y      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A        ã             ¾   +           •okay       usb-phy@0           '               Ø      ð           jref da_ref          	¨           ø   K      usb-phy@700         '              Ø            ð        jref da_ref          Q   _   `   a        ]intr rx_imp tx_imp          	¨           ø   R         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           A        ä             •okay       usb-phy@0           '               Ø      î           jref da_ref          	¨           ø   ?      usb-phy@700         '              Ø            î        jref da_ref          Q   b   c   d        ]intr rx_imp tx_imp          	¨           ø   @         phy@11e80000              mediatek,mt8195-pcie-phy            '    è                 ¦sif         Q   e   f   g   h   i   j   k      G  ]glb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1          ¾   +           	¨            •okay            ø   O      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           '    ú        À         Ø            
  junipro mp           	¨          	  •disabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           '             @         Ø   l          0  …      �             Œ             ‹               �job mmu gpu         	ã   m      (  ¾   +   
   +      +      +      +           	÷core0 core1 core2 core3 core4           •okay            

   n      clock-controller@13fbf000             mediatek,mt8195-mfgcfg          '    ûð                Ë           ø   l      syscon@14000000           mediatek,mt8195-vppsys0 syscon          '                      Ë           
   o                   ø         dma-controller@14001000           mediatek,mt8195-mdp3-rdma           '                     
   o                  
.              
B   p        ¾   +           
O   q   €        Ø            <  ×   o         o         o         o         o              
V         display@14002000              mediatek,mt8195-mdp3-fg         '                      
   o                   Ø             display@14003000              mediatek,mt8195-mdp3-stitch         '     0                
   o      0            Ø            display@14004000              mediatek,mt8195-mdp3-hdr            '     @                
   o      @            Ø      "      display@14005000              mediatek,mt8195-mdp3-aal            '     P                …      F               
   o      P            Ø      
        ¾   +         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '     `                
   o      `            
.    %        Ø            display@14007000              mediatek,mt8195-mdp3-tdshp          '     p                
   o      p            Ø      #      display@14008000              mediatek,mt8195-mdp3-color          '     €                …      I               
   o      €            Ø      $        ¾   +         display@14009000              mediatek,mt8195-mdp3-ovl            '     �                …      J               
   o      �            Ø      %        ¾   +           
O   q   ‚      display@1400a000              mediatek,mt8195-mdp3-padding            '                      
   o                   Ø              ¾   +         display@1400b000              mediatek,mt8195-mdp3-tcc            '     °                
   o      °            Ø            dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '     À                
   o      À            
.    +        Ø              
O   q   ƒ        ¾   +           
V         mutex@1400f000            mediatek,mt8195-vpp-mutex           '     ð                …      P               
   o      ð            Ø              ¾   +         smi@14010000              mediatek,mt8195-smi-sub-common          '                     Ø                          japb smi gals0           
a   r        ¾   +           ø   s      smi@14011000              mediatek,mt8195-smi-sub-common          '                    Ø                          japb smi gals0           
a   r        ¾   +           ø   �      smi@14012000              mediatek,mt8195-smi-common-vpp          '                      Ø                                japb smi gals0 gals1         ¾   +           ø   r      larb@14013000             mediatek,mt8195-smi-larb            '    0                
n           
a   s        Ø                    japb smi         ¾   +           ø   v      iommu@14018000            mediatek,mt8195-iommu-vpp           '    €              8  
   t   u   v   w   x   y   z   {   |   }   ~      €   �        …      R               Ø              jbclk            ‰           ¾   +           ø   q      clock-controller@14e00000             mediatek,mt8195-wpesys          '    à                 Ë           ø         clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         '    à                 Ë         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         '    à0                Ë         larb@14e04000             mediatek,mt8195-smi-larb            '    à@                
n           
a   ‚        Ø                    japb smi         ¾   +           ø   —      larb@14e05000             mediatek,mt8195-smi-larb            '    àP                
n           
a   r        Ø                          japb smi gals            ¾   +           ø   x      syscon@14f00000           mediatek,mt8195-vppsys1 syscon          '    ð                 Ë           
   o   	               ø         mutex@14f01000            mediatek,mt8195-vpp-mutex           '    ð                …      {               
   o   	              Ø      '        ¾   +         larb@14f02000             mediatek,mt8195-smi-larb            '    ð                 
n           
a   ‚        Ø                          japb smi gals            ¾   +           ø   –      larb@14f03000             mediatek,mt8195-smi-larb            '    ð0                
n           
a   s        Ø                          japb smi gals            ¾   +           ø   w      display@14f06000              mediatek,mt8195-mdp3-split          '    ð`                
   o   	  `            Ø            +      ,        ¾   +         display@14f07000              mediatek,mt8195-mdp3-tcc            '    ðp                
   o   	  p            Ø            dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           '    ð€                
   o   	  €            
.  „  ¨        Ø              
O   ƒ            ¾   +           
V         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           '    ð�                
   o   	  �            
.  …  ©        Ø      
        
O   ƒ   ¤        ¾   +           
V         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           '    ð                 
   o   	               
.  †  ª        Ø              
O   q   À        ¾   +           
V         display@14f0b000              mediatek,mt8195-mdp3-fg         '    ð°                
   o   	  °            Ø      	      display@14f0c000              mediatek,mt8195-mdp3-fg         '    ðÀ                
   o   	  À            Ø            display@14f0d000              mediatek,mt8195-mdp3-fg         '    ðÐ                
   o   	  Ð            Ø            display@14f0e000              mediatek,mt8195-mdp3-hdr            '    ðà                
   o   	  à            Ø            display@14f0f000              mediatek,mt8195-mdp3-hdr            '    ðð                
   o   	  ð            Ø            display@14f10000              mediatek,mt8195-mdp3-hdr            '    ñ                 
   o   
               Ø             display@14f11000              mediatek,mt8195-mdp3-aal            '    ñ                …      i               
   o   
              Ø              ¾   +         display@14f12000              mediatek,mt8195-mdp3-aal            '    ñ                 …      j               
   o   
               Ø              ¾   +         display@14f13000              mediatek,mt8195-mdp3-aal            '    ñ0                …      k               
   o   
  0            Ø      !        ¾   +         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '    ñ@                
   o   
  @            
.  �  ¯        Ø            display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '    ñP                
   o   
  P            
.  ‘  °        Ø      $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           '    ñ`                
   o   
  `            
.  ’  ±        Ø      %      display@14f17000              mediatek,mt8195-mdp3-tdshp          '    ñp                
   o   
  p            Ø            display@14f18000              mediatek,mt8195-mdp3-tdshp          '    ñ€                
   o   
  €            Ø      (      display@14f19000              mediatek,mt8195-mdp3-tdshp          '    ñ�                
   o   
  �            Ø      )      display@14f1a000              mediatek,mt8195-mdp3-merge          '    ñ                 
   o   
               Ø              ¾   +         display@14f1b000              mediatek,mt8195-mdp3-merge          '    ñ°                
   o   
  °            Ø              ¾   +         display@14f1c000              mediatek,mt8195-mdp3-color          '    ñÀ                …      t               
   o   
  À            Ø              ¾   +         display@14f1d000              mediatek,mt8195-mdp3-color          '    ñÐ                
   o   
  Ð            …      u               Ø              ¾   +         display@14f1e000              mediatek,mt8195-mdp3-color          '    ñà                …      v               
   o   
  à            Ø              ¾   +         display@14f1f000              mediatek,mt8195-mdp3-ovl            '    ñð                …      w               
   o   
  ð            Ø               ¾   +           
O   ƒ   ¢      display@14f20000              mediatek,mt8195-mdp3-padding            '    ò                 
   o                  Ø              ¾   +         display@14f21000              mediatek,mt8195-mdp3-padding            '    ò                
   o                 Ø              ¾   +         display@14f22000              mediatek,mt8195-mdp3-padding            '    ò                 
   o                  Ø              ¾   +         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '    ò0                
   o     0            
.  Ÿ  «        Ø              
O   ƒ   £        ¾   +           
V         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '    ò@                
   o     @            
.     ¬        Ø              
O   ƒ   ¦        ¾   +           
V         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         '    òP                
   o     P            
.  ¡  ­        Ø              
O   q   Â        ¾   +           
V         clock-controller@15000000             mediatek,mt8195-imgsys          '                      Ë           ø   $      larb@15001000             mediatek,mt8195-smi-larb            '                     
n   	        
a   „        Ø   $       $       $   
        japb smi gals            ¾   +           ø   ˜      smi@15002000              mediatek,mt8195-smi-sub-common          '                      Ø   $      $                 japb smi gals0           
a   r        ¾   +           ø   ‡      smi@15003000              mediatek,mt8195-smi-sub-common          '     0                Ø   $       $       $   
        japb smi gals0           
a   ‚        ¾   +           ø   „      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         '                     Ë           ø   …      larb@15120000             mediatek,mt8195-smi-larb            '                     
n   
        
a   „        Ø   $      …            japb smi         ¾   +           ø   ™      clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          '                     Ë         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         '    "                 Ë           ø   †      larb@15230000             mediatek,mt8195-smi-larb            '    #                 
n           
a   „        Ø   $      †            japb smi         ¾   +           ø   š      clock-controller@15330000             mediatek,mt8195-ipesys          '    3                 Ë           ø   %      larb@15340000             mediatek,mt8195-smi-larb            '    4                 
n           
a   ‡        Ø   %      %           japb smi         ¾   +           ø   y      clock-controller@16000000             mediatek,mt8195-camsys          '                      Ë           ø   &      larb@16001000             mediatek,mt8195-smi-larb            '                     
n           
a   ˆ        Ø   &       &       &           japb smi gals            ¾   +           ø   ›      larb@16002000             mediatek,mt8195-smi-larb            '                      
n           
a   ‰        Ø   &      &           japb smi         ¾   +           ø   z      smi@16004000              mediatek,mt8195-smi-sub-common          '     @                Ø   &       &       &           japb smi gals0           
a   ‚        ¾   +           ø   ˆ      smi@16005000              mediatek,mt8195-smi-sub-common          '     P                Ø   &      &                 japb smi gals0           
a   r        ¾   +           ø   ‰      larb@16012000             mediatek,mt8195-smi-larb            '                     
n           
a   ‰        Ø   Š       Š            japb smi         ¾   +            ø   {      larb@16013000             mediatek,mt8195-smi-larb            '    0                
n           
a   ˆ        Ø   ‹       ‹            japb smi         ¾   +            ø   œ      larb@16014000             mediatek,mt8195-smi-larb            '    @                
n           
a   ‰        Ø   Œ       Œ            japb smi         ¾   +   !        ø   �      larb@16015000             mediatek,mt8195-smi-larb            '    P                
n           
a   ˆ        Ø   �       �            japb smi         ¾   +   !        ø   ¡      clock-controller@1604f000             mediatek,mt8195-camsys_rawa         '    ð                Ë           ø   Š      clock-controller@1606f000             mediatek,mt8195-camsys_yuva         '    ð                Ë           ø   ‹      clock-controller@1608f000             mediatek,mt8195-camsys_rawb         '    ð                Ë           ø   Œ      clock-controller@160af000             mediatek,mt8195-camsys_yuvb         '    
ð                Ë           ø   �      clock-controller@16140000             mediatek,mt8195-camsys_mraw         '                     Ë           ø   Ž      larb@16141000             mediatek,mt8195-smi-larb            '                    
n           
a   ˆ        Ø   &       Ž       &           japb smi gals            ¾   +   "        ø          larb@16142000             mediatek,mt8195-smi-larb            '                     
n           
a   ‰        Ø   Ž       Ž            japb smi         ¾   +   "        ø   €      clock-controller@17200000             mediatek,mt8195-ccusys          '                      Ë           ø   �      larb@17201000             mediatek,mt8195-smi-larb            '                     
n           
a   ‰        Ø   �       �            japb smi         ¾   +           ø   |      video-codec@18000000              mediatek,mt8195-vcodec-dec          
B   p        
O   ƒ                        +            '                   @                A                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         '                       
O   q  à   q  á         Ø      A                  �        jsel vdec lat top                   A        °      �        ¾   +         video-codec@10000             mediatek,mtk-vcodec-lat         '                      …      Ä             0  
O   ƒ      ƒ     ƒ     ƒ     ƒ     ƒ           Ø      A                  �        jsel vdec lat top                   A        °      �        ¾   +         video-codec@25000             mediatek,mtk-vcodec-core            '     P                …      Ã             P  
O   ƒ      ƒ  ¡   ƒ  ¢   ƒ  £   ƒ  ¤   ƒ  ¥   ƒ  ¦   ƒ  §   ƒ  ¨   ƒ  ©         Ø      A                  �        jsel vdec lat top                   A        °      �        ¾   +            larb@1800d000             mediatek,mt8195-smi-larb            '     Ð                
n           
a   ‚        Ø                      japb smi         ¾   +           ø   Ÿ      larb@1800e000             mediatek,mt8195-smi-larb            '     à                
n           
a   �        Ø                     japb smi         ¾   +           ø         clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         '     ð                Ë           ø         larb@1802e000             mediatek,mt8195-smi-larb            '    à                
n           
a   ‚        Ø                      japb smi         ¾   +           ø   ž      clock-controller@1802f000             mediatek,mt8195-vdecsys         '    ð                Ë           ø         larb@1803e000             mediatek,mt8195-smi-larb            '    à                
n           
a   �        Ø                      japb smi         ¾   +           ø   ~      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           '    ð                Ë           ø          clock-controller@190f3000             mediatek,mt8195-apusys_pll          '    0                Ë         clock-controller@1a000000             mediatek,mt8195-vencsys         '                      Ë           ø   !      larb@1a010000             mediatek,mt8195-smi-larb            '                     
n           
a   ‚        Ø   !      !           japb smi         ¾   +           ø   �      video-codec@1a020000              mediatek,mt8195-vcodec-enc          '                   H  
O   ƒ  `   ƒ  a   ƒ  b   ƒ  c   ƒ  d   ƒ  v   ƒ  w   ƒ  x   ƒ  y        …      U               
B   p        Ø   !         	  jvenc_sel                   @        °      �        ¾   +                        +         jpgdec-master             mediatek,mt8195-jpgdec          ¾   +         0  
O   ƒ  m   ƒ  n   ƒ  r   ƒ  s   ƒ  t   ƒ  u                     +            A   jpgdec@1a040000           mediatek,mt8195-jpgdec-hw           '                   0  
O   ƒ  m   ƒ  n   ƒ  r   ƒ  s   ƒ  t   ƒ  u        …      W               Ø   !           jjpgdec          ¾   +         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw           '                   0  
O   ƒ  m   ƒ  n   ƒ  r   ƒ  s   ƒ  t   ƒ  u        …      X               Ø   !           jjpgdec          ¾   +         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw           '                   0  
O   q  �   q  Ž   q  ’   q  “   q  ”   q  •        …      \               Ø   "           jjpgdec          ¾   +            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           '                      Ë           ø   "      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            '                     ×   ‘               Ë           
   ‘                  ø         jpgenc-master             mediatek,mt8195-jpgenc          ¾   +            
O   q  ‡   q  ˆ   q  ‰   q  Œ                     +            A   jpgenc@1a030000           mediatek,mt8195-jpgenc-hw           '                      
O   ƒ  g   ƒ  h   ƒ  i   ƒ  l        …      V               Ø   !           jjpgenc          ¾   +         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw           '                      
O   q  ‡   q  ˆ   q  ‰   q  Œ        …      [               Ø   "           jjpgenc          ¾   +            larb@1b010000             mediatek,mt8195-smi-larb            '                     
n           
a   r        Ø   "      "                  japb smi gals            ¾   +           ø   }      ovl@1c000000              mediatek,mt8195-disp-ovl            '                      …      |               ¾   +           Ø               
O   ƒ           
   ‘                rdma@1c002000             mediatek,mt8195-disp-rdma           '                      …      ~               ¾   +           Ø              
O   ƒ            
   ‘                color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           '     0                …                     ¾   +           Ø              
   ‘     0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           '     @                …      €               ¾   +           Ø              
   ‘     @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           '     P                …      �               ¾   +           Ø              
   ‘     P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           '     `                …      ‚               ¾   +           Ø              
   ‘     `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         '     p                …      ƒ               ¾   +           Ø      	        
   ‘     p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         '     €                …      „               ¾   +           Ø            *   ’        jengine digital hs              ’        	Vdphy          	  •disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            '     �                …      …               ¾   +           Ø              
   ‘     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         '                     …      Ž               ¾   +           Ø            +   “        jengine digital hs              “        	Vdphy          	  •disabled          merge@1c014000            mediatek,mt8195-disp-merge          '    @                …      �               ¾   +           Ø              
   ‘     @          dp-intf@1c015000              mediatek,mt8195-dp-intf         '    P                …      ‘               Ø      ,                    jpixel engine pll          	  •disabled          mutex@1c016000            mediatek,mt8195-disp-mutex          '    `                …      ’               ¾   +           Ø              
   ‘     `            
.  U      larb@1c018000             mediatek,mt8195-smi-larb            '    €                
n            
a   ‚        Ø      (      (              japb smi gals            ¾   +           ø   ”      larb@1c019000             mediatek,mt8195-smi-larb            '    �                
n           
a   r        Ø      (                     japb smi gals            ¾   +           ø   t      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          '                     ×   ‘              
   ‘                  Ë           ™           ø   #      smi@1c01b000              mediatek,mt8195-smi-common-vdo          '    °                 Ø      %      &      )      $        japb smi gals0 gals1         ¾   +           ø   ‚      iommu@1c01f000            mediatek,mt8195-iommu-vdo           '    ð              8  
   ”   •   –   —   ˜   ™   š   ›   œ   �   ž   Ÿ       ¡        …      �               ‰           Ø      '        jbclk            ¾   +           ø   ƒ      mutex@1c101000            mediatek,mt8195-disp-mutex          '                    …      î               ¾   +           Ø   #           
   ‘                 
.  À      larb@1c102000             mediatek,mt8195-smi-larb            '                     
n           
a   ‚        Ø   #       #       #           japb smi gals            ¾   +           ø   •      larb@1c103000             mediatek,mt8195-smi-larb            '    0                
n           
a   r        Ø   #      #                  japb smi gals            ¾   +           ø   u      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           '    @                …      ï               Ø   #           ¾   +           
O   ƒ   @        
   ‘     @            
V         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           '    P                …      ð               Ø   #           ¾   +           
O   q   `        
   ‘     P            
V         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           '    `                …      ñ               Ø   #           ¾   +           
O   ƒ   A        
   ‘     `            
V         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           '    p                …      ò               Ø   #           ¾   +           
O   q   a        
   ‘     p            
V         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           '    €                …      ó               Ø   #           ¾   +           
O   ƒ   B        
   ‘     €            
V         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           '    �                …      ô               Ø   #           ¾   +           
O   q   b        
   ‘     �            
V         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           '                     …      õ               Ø   #           ¾   +           
O   ƒ   C        
   ‘                  
V         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           '    °                …      ö               Ø   #           ¾   +           
O   q   c        
   ‘     °            
V         vpp-merge@1c10c000            mediatek,mt8195-disp-merge          '    À                …      ÷               Ø   #   	   #           jmerge merge_async           ¾   +           
   ‘     À             
Ž        ð   #         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          '    Ð                …      ø               Ø   #   
   #           jmerge merge_async           ¾   +           
   ‘     Ð             
Ž        ð   #         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          '    à                …      ù               Ø   #      #           jmerge merge_async           ¾   +           
   ‘     à             
Ž        ð   #         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          '    ð                …      ú               Ø   #      #           jmerge merge_async           ¾   +           
   ‘     ð             
Ž        ð   #         vpp-merge@1c110000            mediatek,mt8195-disp-merge          '                     …      û               Ø   #      #           jmerge merge_async           ¾   +           
   ‘                   
¢        ð   #         dp-intf@1c113000              mediatek,mt8195-dp-intf         '    0                …                     ¾   +           Ø   #   /   #                 jpixel engine pll          	  •disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  '    @            P            p            �                         °            À              4  ¦mixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  
   ‘     @       ‘     P       ‘     p       ‘     �       ‘             ‘     °       ‘     À          h  Ø   #   %   #       #   #   #   !   #   $   #   "   #   1   #   &   #   '   #   (   #   )   #   *            ƒ  jmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top          ¾   +           
O   q   d   q   e        …                   (  ð   #   3   #   4   #   5   #   6   #   7      E  ÷vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx          '    P        €         Q   ¢        ]dp_calibration_data         ¾   +           …      ¤               
¹  ¤      	  •disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx           '    `        €         Q   ¢        ]dp_calibration_data         ¾   +           …      Ê               
¹  ¤      	  •disabled             thermal-zones      cpu0-thermal            
Ê  è        
Ø   ú        
î   £      trips      trip-alert          
þ L        
  Ð        "passive         ø   ¤      trip-crit           
þ †         
  Ð      	  "critical             cooling-maps       map0               ¤      0     	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            
Ê  è        
Ø   ú        
î   £      trips      trip-alert          
þ L        
  Ð        "passive         ø   ¥      trip-crit           
þ †         
  Ð      	  "critical             cooling-maps       map0               ¥      0     	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            
Ê  è        
Ø   ú        
î   £      trips      trip-alert          
þ L        
  Ð        "passive         ø   ¦      trip-crit           
þ †         
  Ð      	  "critical             cooling-maps       map0               ¦      0     	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            
Ê  è        
Ø   ú        
î   £      trips      trip-alert          
þ L        
  Ð        "passive         ø   §      trip-crit           
þ †         
  Ð      	  "critical             cooling-maps       map0               §      0     	ÿÿÿÿÿÿÿÿ   
ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            
Ê  è        
Ø   ú        
î   £       trips      trip-alert          
þ L        
  Ð        "passive         ø   ¨      trip-crit           
þ †         
  Ð      	  "critical             cooling-maps       map0               ¨      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            
Ê  è        
Ø   ú        
î   £      trips      trip-alert          
þ L        
  Ð        "passive         ø   ©      trip-crit           
þ †         
  Ð      	  "critical             cooling-maps       map0               ©      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            
Ê  è        
Ø   ú        
î   £      trips      trip-alert          
þ L        
  Ð        "passive         ø   ª      trip-crit           
þ †         
  Ð      	  "critical             cooling-maps       map0               ª      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            
Ê  è        
Ø   ú        
î   £      trips      trip-alert          
þ L        
  Ð        "passive         ø   «      trip-crit           
þ †         
  Ð      	  "critical             cooling-maps       map0               «      0     ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            
Ê  è        
Ø   ú        
î   ¬      trips      trip-alert          
þ L        
  Ð        "passive       trip-crit           
þ †         
  Ð      	  "critical                vpu1-thermal            
Ê  è        
Ø   ú        
î   ¬   	   trips      trip-alert          
þ L        
  Ð        "passive       trip-crit           
þ †         
  Ð      	  "critical                gpu-thermal         
Ê  è        
Ø   ú        
î   ¬   
   trips      trip-alert          
þ L        
  Ð        "passive       trip-crit           
þ †         
  Ð      	  "critical                gpu1-thermal            
Ê  è        
Ø   ú        
î   ¬      trips      trip-alert          
þ L        
  Ð        "passive       trip-crit           
þ †         
  Ð      	  "critical                vdec-thermal            
Ê  è        
Ø   ú        
î   ¬      trips      trip-alert          
þ L        
  Ð        "passive       trip-crit           
þ †         
  Ð      	  "critical                img-thermal         
Ê  è        
Ø   ú        
î   ¬      trips      trip-alert          
þ L        
  Ð        "passive       trip-crit           
þ †         
  Ð      	  "critical                infra-thermal           
Ê  è        
Ø   ú        
î   ¬      trips      trip-alert          
þ L        
  Ð        "passive       trip-crit           
þ †         
  Ð      	  "critical                cam0-thermal            
Ê  è        
Ø   ú        
î   ¬      trips      trip-alert          
þ L        
  Ð        "passive       trip-crit           
þ †         
  Ð      	  "critical                cam1-thermal            
Ê  è        
Ø   ú        
î   ¬      trips      trip-alert          
þ L        
  Ð        "passive       trip-crit           
þ †         
  Ð      	  "critical                cpu-thermal         
Ê  è        
Ø            
î   ­   trips      trip-alert          
þ L        
  Ð        "passive       trip-crit           
þ s        
  Ð      	  "critical                pcb-top-thermal         
Ê  è        
Ø            
î   ®   trips      trip-alert          
þ $ø        
  Ð        "passive       trip-crit           
þ L        
  Ð      	  "critical                pcb-bottom-thermal          
Ê  è        
Ø            
î   ¯   trips      trip-alert          
þ $ø        
  Ð        "passive       trip-crit           
þ L        
  Ð      	  "critical                   chosen          )serial0:115200n8          firmware       optee             linaro,optee-tz         2smc          gpio-keys         
    gpio-keys           default            °   key-0           O      j         
  5volume_up           ;   s                 F            leds          
    gpio-leds           default            ±   led-0           O      k            Xkeep            fpower           o            memory@40000000         memory          '    @       €         regulator-vsys            regulator-fixed         ívsys             H         u        ü LK@         LK@        ø   X      reserved-memory                      +            A   optee@43200000           ‡        '    C        À        memory@50000000           shared-dma-pool         '    P       �           ‡        ø   )      memory@53000000           shared-dma-pool         '    S       @        memory@54600000          ‡        '    T`                memory@60000000           shared-dma-pool         '    `                  ‡      memory@62000000           shared-dma-pool         '    b       @           thermal-sensor-0              generic-adc-thermal         n            Ž   ²            šsensor-channel          «ÿÿžX  Âÿÿ±à  ^ÿÿÅh  ìÿÿØð  nÿÿìx  ì      j  ˆ  î  '  {  :˜    N   »  a¨  o  u0  /  ˆ¸   ú  œ@   Î  ¯È   ª  ÃP   �  ÖØ   u  ê`   a  ýè   Q p   D $ø   9 8€   0 L   ) _�   # s    †     š(    ­°    Á8    ÔÀ    èH    ûÐ   
 X   	 "à    6h    Ið           ø   ­      thermal-sensor-1              generic-adc-thermal         n            Ž   ²           šsensor-channel          «ÿÿžX  Âÿÿ±à  ^ÿÿÅh  ìÿÿØð  nÿÿìx  ì      j  ˆ  î  '  {  :˜    N   »  a¨  o  u0  /  ˆ¸   ú  œ@   Î  ¯È   ª  ÃP   �  ÖØ   u  ê`   a  ýè   Q p   D $ø   9 8€   0 L   ) _�   # s    †     š(    ­°    Á8    ÔÀ    èH    ûÐ   
 X   	 "à    6h    Ið           ø   ®      thermal-sensor-2              generic-adc-thermal         n            Ž   ²           šsensor-channel          «ÿÿžX  Âÿÿ±à  ^ÿÿÅh  ìÿÿØð  nÿÿìx  ì      j  ˆ  î  '  {  :˜    N   »  a¨  o  u0  /  ˆ¸   ú  œ@   Î  ¯È   ª  ÃP   �  ÖØ   u  ê`   a  ýè   Q p   D $ø   9 8€   0 L   ) _�   # s    †     š(    ­°    Á8    ÔÀ    èH    ûÐ   
 X   	 "à    6h    Ið           ø   ¯         	compatible interrupt-parent #address-cells #size-cells model dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 mmc0 mmc1 serial0 serial1 serial2 serial3 serial4 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges pinmux drive-strength input-enable output-high input-disable bias-disable bias-pull-up drive-strength-microamp bias-pull-down #power-domain-cells clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells memory-region firmware-name power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-names pinctrl-0 uart-has-rtscts mediatek,pad-select spi-max-frequency nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 reset-assert-us reset-deassert-us reset-gpios snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup dr_mode vusb33-supply bus-width hs400-ds-delay cap-mmc-highspeed cap-mmc-hw-reset mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable vmmc-supply vqmmc-supply cd-gpios cap-sd-highspeed sd-uhs-sdr50 sd-uhs-sdr104 no-mmc mediatek,u3p-dis-msk bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map spi-rx-bus-width spi-tx-bus-width bits #phy-cells LDO_VIN1-supply LDO_VIN2-supply LDO_VIN3-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path label linux,code debounce-interval default-state function color regulator-boot-on no-map io-channels io-channel-names temperature-lookup-table 