Ðþí T”   8 H   (            x Gä                             .    radxa,nio-12l mediatek,mt8395 mediatek,mt8195                                    +            7Radxa NIO 12L         	   =embedded       aliases          J/soc/dp-intf@1c015000            S/soc/dp-intf@1c113000            \/soc/mailbox@10320000            a/soc/mailbox@10330000            f/soc/hdr-engine@1c114000             m/soc/mutex@1c016000          t/soc/mutex@1c101000          {/soc/vpp-merge@1c10c000          ‚/soc/vpp-merge@1c10d000          ‰/soc/vpp-merge@1c10e000          �/soc/vpp-merge@1c10f000          —/soc/vpp-merge@1c110000          ž/soc/dma-controller@1c104000             ©/soc/dma-controller@1c105000             ´/soc/dma-controller@1c106000             ¿/soc/dma-controller@1c107000             Ê/soc/dma-controller@1c108000             Õ/soc/dma-controller@1c109000             à/soc/dma-controller@1c10a000             ë/soc/dma-controller@1c10b000             ö/soc/i2c@11e02000            û/soc/i2c@11e03000            /soc/i2c@11e04000           /soc/i2c@11e00000           
/soc/i2c@11e01000           /soc/ethernet@11021000          /soc/serial@11001100            !/soc/serial@11001200            )/soc/spi@11010000           ./soc/spi@11012000         cpus                         +       cpu@0           3cpu           arm,cortex-a55          ?            Cpsci            Q               eec3@        u  4        ˆ              ˜  €         ¥   @        ·   €        Ä  €         Ñ   @        ã   €        ð                                          cpu@100         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4        ˆ              ˜  €         ¥   @        ·   €        Ä  €         Ñ   @        ã   €        ð                                          cpu@200         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4        ˆ              ˜  €         ¥   @        ·   €        Ä  €         Ñ   @        ã   €        ð                                          cpu@300         3cpu           arm,cortex-a55          ?           Cpsci            Q               eec3@        u  4        ˆ              ˜  €         ¥   @        ·   €        Ä  €         Ñ   @        ã   €        ð                                          cpu@400         3cpu           arm,cortex-a78          ?           Cpsci            Q              e�fÔÀ        u           ˆ              ˜           ¥   @        ·           Ä           Ñ   @        ã           ð   	                      
                 cpu@500         3cpu           arm,cortex-a78          ?           Cpsci            Q              e�fÔÀ        u           ˆ              ˜           ¥   @        ·           Ä           Ñ   @        ã           ð   	                      
                 cpu@600         3cpu           arm,cortex-a78          ?           Cpsci            Q              e�fÔÀ        u           ˆ              ˜           ¥   @        ·           Ä           Ñ   @        ã           ð   	                      
                 cpu@700         3cpu           arm,cortex-a78          ?           Cpsci            Q              e�fÔÀ        u           ˆ              ˜           ¥   @        ·           Ä           Ñ   @        ã           ð   	                      
                 cpu-map    cluster0       core0           #         core1           #         core2           #         core3           #         core4           #         core5           #         core6           #         core7           #               idle-states         'psci       cpu-retention-l           arm,idle-state          4           K        \   2        m   _        }  D                 cpu-retention-b           arm,idle-state          4           K        \   -        m   Œ        }  ä                 cpu-off-l             arm,idle-state          4          K        \   7        m   ›        }  H                 cpu-off-b             arm,idle-state          4          K        \   2        m   È        }  è                    l2-cache0             cache           Ž           š           §   @        ¹           ð            š                 l2-cache1             cache           Ž           š           §   @        ¹           ð            š           	      l3-cache              cache           Ž           š            §   @        ¹            š                    dsu-pmu           arm,dsu-pmu         ¨                       ³                                ¸fail          dmic-codec            dmic-codec          ¿           Ì   2      mt8195-sound            Ü         	  ¸disabled          fixed-factor-clock-13m            fixed-factor-clock          î            û                                 clk13m             ,      oscillator-26m            fixed-clock         î            eŒº€        clk26m                   oscillator-32k            fixed-clock         î            e  €         clk32k        performance-controller@11bc10             mediatek,cpufreq-hw          ?     ¼            ½0               *                    opp-table-gpu             operating-points-v2          D           u   opp-390000000           O    >í€        V 	‰h      opp-410000000           O    p€        V 	¡Ò      opp-431000000           O    °‰À        V 	¡Ò      opp-473000000           O    1h@        V 	º<      opp-515000000           O    ²FÀ        V 	º<      opp-556000000           O    !#ã         V 	Ò¦      opp-598000000           O    #¤Á€        V 	ë      opp-640000000           O    &%          V 	ë      opp-670000000           O    'ïc€        V 
ä      opp-700000000           O    )¹'         V 
L¸      opp-730000000           O    +‚ê€        V 
}Œ      opp-760000000           O    -L®         V 
®`      opp-790000000           O    /q€        V 
ß4      opp-820000000           O    0à5         V       opp-850000000           O    2©ø€        V @Ü      opp-880000000           O    4s¼         V q°         pmu-a55           arm,cortex-a55-pmu                      ¨                  pmu-a78           arm,cortex-a78-pmu                      ¨                  psci              arm,psci-1.0            Jsmc       timer             arm,armv8-timer                   @  ¨                                             
             soc                      +             simple-bus           d        k                          interrupt-controller@c000000              arm,gic-v3          v           ‡                        ž         ?                                    ¨      	                     ppi-partitions     interrupt-partition-0           ³                             interrupt-partition-1           ³                                   syscon@10000000            mediatek,mt8195-topckgen syscon         ?                      î                    syscon@10001000       #    mediatek,mt8195-infracfg_ao syscon          ?                     î           ¼                    syscon@10003000           mediatek,mt8195-pericfg syscon          ?     0                î              B      pinctrl@10005000              mediatek,mt8195-pinctrl       €  ?     P            Ñ             Ó             Ô             â             ë             ô              °              B  Éiocfg0 iocfg_bm iocfg_bl iocfg_br iocfg_lm iocfg_rb iocfg_tl eint            Ó        ã           ï              �         ž        ¨       ë               v            û              eth-default-pins               >   pins-cc           U  V  W  X        &         pins-mdio             Y  Z         5      pins-power            [   \          B      pins-rst              ]       pins-rxd              Q  R  S  T      pins-txd              M  N  O  P        &            eth-sleep-pins             ?   pins-cc           U   V   W   X       pins-mdio             Y   Z          N         [      pins-rxd              Q   R   S   T       pins-txd              M   N   O   P          i2c2-pins              c   pins-bus                        i  è        &           v  è         i2c4-pins              f   pins-bus                        i  è        v  è         i2c6-pins              \   pins                         N         mmc0-default-pins              G   pins-clk              z        Ž   f        &         pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y        i   e        &            5      pins-rst              x        i   e        &            mmc0-uhs-pins              H   pins-clk              z        Ž   f        &         pins-cmd-dat          $    ~  }  |  {  w  v  u  t  y        i   e        &            5      pins-ds                   Ž   f        &         pins-rst              x        i   e        &            mmc1-default-pins              K   pins-clk              o        Ž   f        &         pins-cmd-dat              n  p  q  r  s        i   e        &            5         mmc1-detect-pins               L   pins-insert           �          i         mt6360-pins            ]   pins-irq              d   e          5         i         pcie0-default-pins             W   pins-bus                           i         pcie1-default-pins             Z   pins-bus                            N         spi1-default-pins              8   pins-bus              ˆ  ‰  Š  ‹         N         spi2-default-pins              9   pins-bus              Œ  �  Ž  �         N         uart0-pins             3   pins-bus              b  c         uart1-pins             4   pins-bus              f  g         usb3p0-default-pins            C   pins-vbus             ?         5         usb2p0-default-pins            R   pins-iddig            ‚         5         i      pins-vbus             ƒ         �         wifi-vreg-pins             ´   pins-wifi-pmu-en              A          B      pins-wifi-vreg-en             C             syscon@10006000       )    mediatek,mt8195-scpsys syscon simple-mfd            ?     `           power-controller          !    mediatek,mt8195-power-controller                         +            ¨              /   power-domain@8          ?                        +            ¨           ¼      power-domain@9          ?   	        û                    Êmfg alt         Ö                        +            ¨           ¼      power-domain@10         ?   
        ¨          power-domain@11         ?           ¨          power-domain@12         ?           ¨          power-domain@13         ?           ¨          power-domain@14         ?           ¨                power-domain@15         ?         Ø  û                        	      @      A      K      à                                                                                                                          Êvppsys vppsys1 vppsys2 vppsys3 vppsys4 vppsys5 vppsys6 vppsys7 vppsys0-0 vppsys0-1 vppsys0-2 vppsys0-3 vppsys0-4 vppsys0-5 vppsys0-6 vppsys0-7 vppsys0-8 vppsys0-9 vppsys0-10 vppsys0-11 vppsys0-12 vppsys0-13 vppsys0-14 vppsys0-15 vppsys0-16 vppsys0-17 vppsys0-18           Ö                        +            ¨      power-domain@16         ?         8  û      â      $      %      &      '      (      )      D  Êvdosys0 vdosys0-0 vdosys0-1 vdosys0-2 vdosys0-3 vdosys0-4 vdosys0-5         Ö                        +            ¨      power-domain@17         ?           û      á                      Êvppsys1 vppsys1-0 vppsys1-1         Ö           ¨          power-domain@22         ?            û   !      !      !      !         $  Êwepsys-0 wepsys-1 wepsys-2 wepsys-3         Ö           ¨          power-domain@23         ?           û   "            Êvdec0-0         Ö                        +            ¨       power-domain@24         ?           û   #            Êvdec1-0         Ö           ¨          power-domain@25         ?           û   $            Êvdec2-0         Ö           ¨             power-domain@26         ?           û   %            Êvenc0-larb          Ö                        +            ¨       power-domain@27         ?           û   &            Êvenc1-larb          Ö           ¨             power-domain@18         ?            û      ã   '       '      '         &  Êvdosys1 vdosys1-0 vdosys1-1 vdosys1-2           Ö                        +            ¨      power-domain@19         ?           Ö           ¨          power-domain@20         ?           Ö           ¨          power-domain@21         ?           û      Q        Êhdmi_tx         ¨             power-domain@28         ?           û   (       (   
        Êimg-0 img-1         Ö                        +            ¨      power-domain@29         ?           ¨          power-domain@30         ?           û         (      )           Êipe ipe-0 ipe-1         Ö           ¨             power-domain@31         ?         (  û   *       *      *      *      *           Êcam-0 cam-1 cam-2 cam-3 cam-4           Ö                        +            ¨      power-domain@32         ?            ¨          power-domain@33         ?   !        ¨          power-domain@34         ?   "        ¨                   power-domain@0          ?            Ö           ¨          power-domain@1          ?           Ö           ¨          power-domain@2          ?           ¨          power-domain@3          ?           ¨          power-domain@4          ?           û      5      7        Êcsi_rx_top csi_rx_top1          ¨          power-domain@5          ?           û   +           Êether           ¨          power-domain@6          ?           û      X      n        Êadsp adsp1                       +            Ö           ¨      power-domain@7          ?            û      g      "      n      2        Êaudio audio1 audio2 audio3          Ö           ¨                   watchdog@10007000             mediatek,mt8195-wdt          è        ?     p                ¼              2      syscon@1000c000       "    mediatek,mt8195-apmixedsys syscon           ?     À                î                    timer@10017000        ,    mediatek,mt8195-timer mediatek,mt6765-timer         ?    p                ¨      	               û   ,      pwrap@10024000            mediatek,mt8195-pwrap syscon            ?    @                Épwrap           ¨       ó               û                   	  Êspi wrap                   $              Ë   pmic              mediatek,mt6359          ž        v           '      Þ      adc           mediatek,mt6359-auxadc          ;         mt6359codec       regulators            mediatek,mt6359-regulator      buck_vs1            Mvs1         \ 5         t !‘À        Œ             ¨      buck_vgpu11         Mvgpu11          \ €        t 7        ¼  ˆ        Œ   È        Ñ                   ¨      buck_vmodem         Mvmodem          \ €        t Èà        ¼  *        Œ   È      buck_vpu            Mvpu         \ €        t 7        ¼  ˆ        Œ   È        Ñ                   ¨      buck_vcore          Mvcore           \ €        t Ö         ¼  ˆ        Œ   È        Ñ                   ¨                 buck_vs2            Mvs2         \ 5         t j         Œ             ¨      buck_vpa            Mvpa         \ ¡         t 7±Ð        Œ  ,      buck_vproc2         Mvproc2          \ €        t 7        ¼  L        Œ   È        Ñ                   ¨      buck_vproc1         Mvproc1          \ €        t 7        ¼  L        Œ   È        Ñ                   ¨      buck_vcore_sshub            Mvcore_sshub         \ €        t 7      buck_vgpu11_sshub           Mvgpu11_sshub            \ €        t 7      ldo_vaud18          Mvaud18          \ w@        t w@        Œ   ð         ¨      ldo_vsim1           Mvsim1           \ ð         t /M`      ldo_vibr            Mvibr            \ O€        t 2Z            d      ldo_vrf12           Mvrf12           \ Èà        t Ö          ¨      ldo_vusb            Mvusb            \ -ÆÀ        t -ÆÀ        Œ  À         ¨           D      ldo_vsram_proc2         Mvsram_proc2         \ ¡         t ½¶        ¼  L        Œ   ð         ¨      ldo_vio18           Mvio18           \ ð         t ýà        Œ  À         ¨      ldo_vcamio          Mvcamio          \ ð         t ýà         ¨      ldo_vcn18           Mvcn18           \ w@        t w@        Œ   ð      ldo_vfe28           Mvfe28           \ *¹€        t *¹€        Œ   x      ldo_vcn13           Mvcn13           \ »         t Ö       ldo_vcn33_1_bt          Mvcn33_1_bt          \ *¹€        t 5gà      ldo_vcn33_1_wifi            Mvcn33_1_wifi            \ *¹€        t 5gà      ldo_vaux18          Mvaux18          \ w@        t w@        Œ   ð         ¨      ldo_vsram_others            Mvsram_others            \ q°        t q°        ¼  ˆ        Œ   ð                 ldo_vefuse          Mvefuse          \ ð         t „€      ldo_vxo22           Mvxo22           \ w@        t !‘À         ¨      ldo_vrfck           Mvrfck           \ ã`        t ð       ldo_vrfck_1         Mvrfck           \ ëÀ        t j       ldo_vbif28          Mvbif28          \ *¹€        t *¹€        Œ   ð      ldo_vio28           Mvio28           \ *¹€        t 2Z          ¨      ldo_vemc            Mvemc            \ ,@         t 2Z       ldo_vemc_1          Mvemc            \ &%         t 2Z            I      ldo_vcn33_2_bt          Mvcn33_2_bt          \ 2Z         t 2Z       ldo_vcn33_2_wifi            Mvcn33_2_wifi            \ *¹€        t 5gà      ldo_va12            Mva12            \ O€        t Ö          ¨      ldo_va09            Mva09            \ 5         t O€      ldo_vrf18           Mvrf18           \ ð         t žP      ldo_vsram_md          	  Mvsram_md            \ ¡         t ½¶        ¼  *        Œ   ð         ¨      ldo_vufs            Mvufs            \ ð         t ýà           J      ldo_vm18            Mvm18            \ ð         t ýà         ¨      ldo_vbbck           Mvbbck           \ Èà        t O€         ¨      ldo_vsram_proc1         Mvsram_proc1         \ ¡         t ½¶        ¼  L        Œ   ð         ¨      ldo_vsim2           Mvsim2           \ ð         t /M`      ldo_vsram_others_sshub          Mvsram_others_sshub          \ ¡         t ½¶         rtc           mediatek,mt6358-rtc             spmi@10027000             mediatek,mt8195-spmi             ?    p            �                Épmif spmimst            û                   E      (  Êpmif_sys_ck pmif_tmr_ck spmimst_clk_mux                $              Ë                     +       pmic@6            mediatek,mt6315-regulator           ?          regulators     vbuck1          MVbcpu           \ “à        t 7        Œ           Ñ                   ¨           
            pmic@7            mediatek,mt6315-regulator           ?          regulators     vbuck1          MVgpu            \ “à        t 7        Œ           Ñ                                    infra-iommu@10315000              mediatek,mt8195-iommu-infra         ?    1P       P       P  ¨                                                                         é              T      mailbox@10320000              mediatek,mt8195-gce         ?    2        @         ¨       â               ö           û                 ˜      mailbox@10330000              mediatek,mt8195-gce         ?    3        @         ¨       ä               ö           û                 v      scp@10500000              mediatek,mt8195-scp       0  ?    P             r             p        €         Ésram cfg l1tcm          ¨      Î               ¸okay               -           w      clock-controller@10720000             mediatek,mt8195-scp_adsp            ?    r                 î              .      dsp@10803000              mediatek,mt8195-dsp          ?    €0            „               	  Écfg sram          ,  û      X         n      Š   .          #      K  Êadsp_sel clk26m_ck audio_local_bus mainpll_d7_d2 scp_adsp_audiodsp audio_h             /           rx tx           )   0   1      	  ¸disabled          mailbox@10816000              mediatek,mt8195-adsp-mbox           ö            ?    �`                ¨      ¾                  0      mailbox@10817000              mediatek,mt8195-adsp-mbox           ö            ?    �p                ¨      ¿                  1      mt8195-afe-pcm@10890000           mediatek,mt8195-audio           ?    ‰                 0              /           ¨      6               B   2         	  Iaudiosys          ”  û                     Ú      Û      Ü      Ý      ß      g      "      #      n      e      a      b      c      d      2   .          ó  Êclk26m apll1_ck apll2_ck apll12_div0 apll12_div1 apll12_div2 apll12_div3 apll12_div9 a1sys_hp_sel aud_intbus_sel audio_h_sel audio_local_bus_sel dptx_m_sel i2so1_m_sel i2so2_m_sel i2si1_m_sel i2si2_m_sel infra_ao_audio_26m_b scp_adsp_audiodsp        	  ¸disabled                     serial@11001100       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                     ¨       �               û               	  Êbaud bus            ¸okay            U   3        _default       serial@11001200       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                     ¨       Ž               û               	  Êbaud bus            ¸okay            U   4        _default       serial@11001300       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                     ¨       �               û               	  Êbaud bus          	  ¸disabled          serial@11001400       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                     ¨      Ó               û               	  Êbaud bus          	  ¸disabled          serial@11001500       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                     ¨      Ô               û               	  Êbaud bus          	  ¸disabled          serial@11001600       *    mediatek,mt8195-uart mediatek,mt6577-uart           ?                     ¨      Õ               û               	  Êbaud bus          	  ¸disabled          auxadc@11002000       .    mediatek,mt8195-auxadc mediatek,mt8173-auxadc           ?                      û              Êmain            ;         	  ¸disabled          syscon@11003000       "    mediatek,mt8195-pericfg_ao syscon           ?     0                î              +      spi@1100a000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                      ¨       ¿               û      ™                    Êparent-clk sel-clk spi-clk        	  ¸disabled          thermal-sensor@1100b000           mediatek,mt8195-lvts-ap         ?     °                ¨       ©               û              B               m   5   6      $  ylvts-calib-data-1 lvts-calib-data-2         Š              ³      svs@1100bc00              mediatek,mt8195-svs         ?     ¼                ¨       Ç               û              Êmain            m   7   5      (  ysvs-calibration-data t-calibration-data         B              Isvs_rst       pwm@1100e000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           ?     à                ¨       Ë                  /                       û      *      0        Êmain mm       	  ¸disabled          pwm@1100f000          2    mediatek,mt8195-disp-pwm mediatek,mt8183-disp-pwm           ?     ð                ¨                                 û      +      N        Êmain mm       	  ¸disabled          spi@11010000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                     ¨       À               û      ™            3        Êparent-clk sel-clk spi-clk          ¸okay            U   8        _default         «          spi@11012000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?                     ¨       Á               û      ™            4        Êparent-clk sel-clk spi-clk          ¸okay            U   9        _default         «          spi@11013000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?    0                ¨       Â               û      ™            5        Êparent-clk sel-clk spi-clk        	  ¸disabled          spi@11018000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?    €                ¨       Ã               û      ™            <        Êparent-clk sel-clk spi-clk        	  ¸disabled          spi@11019000          (    mediatek,mt8195-spi mediatek,mt6765-spi                      +            ?    �                ¨       Ä               û      ™            =        Êparent-clk sel-clk spi-clk        	  ¸disabled          spi@1101d000              mediatek,mt8195-spi-slave           ?    Ð                ¨       Å               û      R        Êspi                              ˜      	  ¸disabled          spi@1101e000              mediatek,mt8195-spi-slave           ?    à                ¨       Æ               û      S        Êspi                              ˜      	  ¸disabled          ethernet@11021000         &    mediatek,mt8195-gmac snps,dwmac-5.10a           ?           @         ¨      Ì               ¿macirq        .  Êaxi apb mac_main ptp_ref rmii_internal mac_cg         0  û   +       +         R      S      T   +                  R      S      T              Â      Ã      Ä           /           Ï           à   :        ð   ;           <                   !           ,            ¸okay            9rgmii-rxid          B   =        _default sleep           U   >        M   ?        W  î         l        }      ]            �      N  †    mdio              snps,dwmac-mdio                      +       ethernet-phy@1            ethernet-phy-id001c.c916            ?              =         stmmac-axi-config           ¢           ²           Â                                    :      rx-queues-config            Ì            â           ;   queue0           ó                  queue1           ó                  queue2           ó                  queue3           ó                     tx-queues-config                        4           <   queue0          F            ó        R          queue1          F            ó        R         queue2          F            ó        R         queue3          F            ó        R               usb@11201000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?            -ÿ     >              	  Émac ippc            d                     ?                      +           ¨       €               û      /      í      B        Êsys_ck ref_ck mcu_ck            `   @      A            e        s   B      g        ¸okay            _default         U   C        Šhost             £        ³   D   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       Émac         ¨       �                      ,      -              –      –      $  û      /      í               B      $  Êsys_ck ref_ck mcu_ck dma_ck xhci_ck         ¸okay            Á   E      port       endpoint            Í   F           `            mmc@11230000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    #             õ                 ¨       ƒ               û                          Êsource hclk source_cg           ¸okay            _default state_uhs           U   G        M   H        Ý           çëÂ         õ L         	         	         	'         	6         	E         	M         	S        	a   I        	m   J      mmc@11240000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    $             Ç                 ¨       ‡               û                  $        Êsource hclk source_cg                                ¿        ¸okay            _default state_uhs           U   K   L        M   K        Ý           çëÂ          	z        	‹      �            	”         	E         	›         	¨        	a   M        	m   N      mmc@11250000          (    mediatek,mt8195-mmc mediatek,mt8183-mmc          ?    %             æ                 ¨       ˆ               û                   I        Êsource hclk source_cg                                 ¿      	  ¸disabled          thermal-sensor@11278000           mediatek,mt8195-lvts-mcu            ?    '€                ¨       ª               û              B              m   5   6      $  ylvts-calib-data-1 lvts-calib-data-2         Š              ª      usb@11290000          '    mediatek,mt8195-xhci mediatek,mtk-xhci           ?    )             )>              	  Émac ippc            ¨                     `   O                  .      /              –      –      $  û   +         ï            +         $  Êsys_ck ref_ck mcu_ck dma_ck xhci_ck         s   B      h         e        ¸okay             	¶        ³   D        Á   P        	Ç         usb@112a1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?    *       -ÿ    *>              	  Émac ippc            d            *        ?                      +           ¨                            0              –        û   +         ñ   +           Êsys_ck ref_ck mcu_ck            `   Q            e        s   B      i        ¸okay            _default         U   R        ³   D   usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       Émac         ¨                            1              –        û   +           Êsys_ck          ¸okay            Á   P         usb@112b1000          #    mediatek,mt8195-mtu3 mediatek,mtu3           ?    +       -ÿ    +>              	  Émac ippc            d            +        ?                      +           ¨                            2              –        û   +         ó   +   	        Êsys_ck ref_ck mcu_ck            `   S            e        s   B      j      	  ¸disabled       usb@0         '    mediatek,mt8195-xhci mediatek,mtk-xhci          ?                       Émac         ¨                            3              –        û   +   	        Êsys_ck        	  ¸disabled             pcie@112f0000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           3pci                      +           ?    /        @       	  Épcie-mac            ¨                     	Ü       ÿ      8  d�                           ‚                       à          	æ       T              	ð          0  û      V      #      &      +      K   +         /  Êpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                 G                      `   U      	  	ÿpcie-phy               /            v           
	                     `  
                  V                      V                     V                     V           ¸okay            _default         U   W   interrupt-controller             ž                     v              V         pcie@112f8000         *    mediatek,mt8195-pcie mediatek,mt8192-pcie           3pci                      +           ?    /€       @       	  Épcie-mac            ¨                     	Ü       ÿ      8  d�       $       $           ‚       $       $       à          	æ       T              	ð          (  û      W         X         Q   +         /  Êpl_250m tl_26m tl_96m tl_32k peri_26m peri_mem                 H                      `   X         	  	ÿpcie-phy               /           v           
	                     `  
                  Y                      Y                     Y                     Y           ¸okay            _default         U   Z   interrupt-controller             ž                     v              Y         spi@1132c000          (    mediatek,mt8195-nor mediatek,mt8173-nor         ?    2À                ¨      9               û      o   +      +           Êspi sf axi                       +          	  ¸disabled          efuse@11c10000        %    mediatek,mt8195-efuse mediatek,efuse            ?    Á                              +      usb3-tx-imp@184,1           ?  „           
*                  l      usb3-rx-imp@184,2           ?  „           
*                 k      usb3-intr@185           ?  …           
*                 j      usb3-tx-imp@186,1           ?  †           
*                  i      usb3-rx-imp@186,2           ?  †           
*                 h      usb3-intr@187           ?  ‡           
*                 g      usb2-intr-p0@188,1          ?  ˆ           
*             usb2-intr-p1@188,2          ?  ˆ           
*            usb2-intr-p2@189,1          ?  ‰           
*            usb2-intr-p3@189,2          ?  ‰           
*            pciephy-rx-ln1@190,1            ?  �           
*                  s      pciephy-tx-ln1-nmos@190,2           ?  �           
*                 r      pciephy-tx-ln1-pmos@191,1           ?  ‘           
*                  q      pciephy-rx-ln0@191,2            ?  ‘           
*                 p      pciephy-tx-ln0-nmos@192,1           ?  ’           
*                  o      pciephy-tx-ln0-pmos@192,2           ?  ’           
*                 n      pciephy-glb-intr@193            ?  “           
*                  m      dp-data@1ac         ?  ¬              ©      lvts1-calib@1bc         ?  ¼              5      lvts2-calib@1d0         ?  Ð   8           6      svs-calib@580           ?  €   d           7      socinfo-data1@7a0           ?               t-phy@11c40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           d        Ä             ¸okay       usb-phy@0           ?               û      ò        Êref         
/              Q         t-phy@11c50000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           d        Å           	  ¸disabled       usb-phy@0           ?               û      ô        Êref         
/              S         dsi-phy@11c80000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         ?    È                 û           mipi_tx0_pll            î            
/          	  ¸disabled               ™      dsi-phy@11c90000          0    mediatek,mt8195-mipi-tx mediatek,mt8183-mipi-tx         ?    É                 û           mipi_tx1_pll            î            
/          	  ¸disabled               š      i2c@11d00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    Ð             "€       €        ¨       š                          û   [          ;      	  Êmain dma                         +          	  ¸disabled          i2c@11d01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    Ð            "        €        ¨       ›                          û   [         ;      	  Êmain dma                         +            ¸okay            e €        U   \        _default    pmic@34           mediatek,mt6360         ?   4        '      e           ¿IRQB             ž        v           U   ]   charger           mediatek,mt6360-chg         
: Ý@    usb-otg-vbus-regulator          Musb-otg-vbus            \ C…(        t Xáè           E         regulator             mediatek,mt6360-regulator           
S   ^        
c   _   buck1         	  Memi_vdd2            \ “à        t Ö         Ñ                   ¨      buck2         	  Memi_vddq            \ “à        t Ö         Ñ                   ¨           _      ldo1            Mext_lcd_3v3         \ 2Z         t 2Z         Ñ                ¨      ldo2            Mpanel1_p1v8         \ w@        t w@        Ñ             ldo3            Mvmc_pmu         \ O€        t 6î€        Ñ                  N      ldo5          	  Mvmch_pmu            \ 2Z         t 2Z         Ñ                ¨           M      ldo6            Mmt6360_ldo6         \ ¡         t           Ñ             ldo7            Memi_vmddr_en            \ ¡         t           Ñ                ¨         typec             mediatek,mt6360-tcpc            '      d           ¿PD_IRQB    connector             usb-c-connector         
sUSB-C           
ydual            
ƒ ˜–€        
•dual            
 sink            
¯"�d        
»"‘,   ports                        +       port@0          ?       endpoint            Í   `           F         port@2          ?      endpoint            Í   a           e                        i2c@11d02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    Ð             "€       €        ¨       œ                          û   [         ;      	  Êmain dma                         +          	  ¸disabled          clock-controller@11d03000             mediatek,mt8195-imp_iic_wrap_s          ?    Ð0                î              [      i2c@11e00000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    à             " €       €        ¨       �                          û   b          ;      	  Êmain dma                         +          	  ¸disabled          i2c@11e01000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    à            "        €        ¨       “                          û   b         ;      	  Êmain dma                         +          	  ¸disabled          i2c@11e02000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    à             "€       €        ¨       –                          û   b         ;      	  Êmain dma                         +            ¸okay            e €        U   c        _default    typec-mux@48              ite,it5205          ?   H         
Å         
Ñ        
ä   d   port       endpoint            Í   e           a               i2c@11e03000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    à0            "€       €        ¨       ˜                          û   b         ;      	  Êmain dma                         +          	  ¸disabled          i2c@11e04000          (    mediatek,mt8195-i2c mediatek,mt8192-i2c          ?    à@            "        €        ¨       ™                          û   b         ;      	  Êmain dma                         +            ¸okay            e €        U   f        _default       clock-controller@11e05000             mediatek,mt8195-imp_iic_wrap_w          ?    àP                î              b      t-phy@11e30000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           d        ã                /           ¸okay       usb-phy@0           ?               û      ð           Êref da_ref          
/              O      usb-phy@700         ?              û            ð        Êref da_ref          m   g   h   i        yintr rx_imp tx_imp          
/              X         t-phy@11e40000        .    mediatek,mt8195-tphy mediatek,generic-tphy-v3                        +           d        ä             ¸okay       usb-phy@0           ?               û      î           Êref da_ref          
/              @      usb-phy@700         ?              û            î        Êref da_ref          m   j   k   l        yintr rx_imp tx_imp          
/              A         phy@11e80000              mediatek,mt8195-pcie-phy            ?    è                 Ésif         m   m   n   o   p   q   r   s      G  yglb_intr tx_ln0_pmos tx_ln0_nmos rx_ln0 tx_ln1_pmos tx_ln1_nmos rx_ln1             /           
/            ¸okay               U      ufs-phy@11fa0000          .    mediatek,mt8195-ufsphy mediatek,mt8183-ufsphy           ?    ú        À         û            
  Êunipro mp           
/          	  ¸disabled          gpu@13000000          >    mediatek,mt8195-mali mediatek,mt8192-mali arm,mali-valhall-jm           ?             @         û   t          0  ¨      �             Œ             ‹               ¿job mmu gpu         
ï   u      (     /   
   /      /      /      /           core0 core1 core2 core3 core4           ¸okay                     clock-controller@13fbf000             mediatek,mt8195-mfgcfg          ?    ûð                î              t      syscon@14000000           mediatek,mt8195-vppsys0 syscon          ?                      î           "   v                            dma-controller@14001000           mediatek,mt8195-mdp3-rdma           ?                     "   v                  :              N   w           /           [   x   €        û            <  )   v         v         v         v         v              b         display@14002000              mediatek,mt8195-mdp3-fg         ?                      "   v                   û             display@14003000              mediatek,mt8195-mdp3-stitch         ?     0                "   v      0            û            display@14004000              mediatek,mt8195-mdp3-hdr            ?     @                "   v      @            û      "      display@14005000              mediatek,mt8195-mdp3-aal            ?     P                ¨      F               "   v      P            û      
           /         display@14006000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?     `                "   v      `            :    %        û            display@14007000              mediatek,mt8195-mdp3-tdshp          ?     p                "   v      p            û      #      display@14008000              mediatek,mt8195-mdp3-color          ?     €                ¨      I               "   v      €            û      $           /         display@14009000              mediatek,mt8195-mdp3-ovl            ?     �                ¨      J               "   v      �            û      %           /           [   x   ‚      display@1400a000              mediatek,mt8195-mdp3-padding            ?                      "   v                   û                 /         display@1400b000              mediatek,mt8195-mdp3-tcc            ?     °                "   v      °            û            dma-controller@1400c000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?     À                "   v      À            :    +        û              [   x   ƒ           /           b         mutex@1400f000            mediatek,mt8195-vpp-mutex           ?     ð                ¨      P               "   v      ð            û                 /         smi@14010000              mediatek,mt8195-smi-sub-common          ?                     û                          Êapb smi gals0           m   y           /              z      smi@14011000              mediatek,mt8195-smi-sub-common          ?                    û                          Êapb smi gals0           m   y           /              —      smi@14012000              mediatek,mt8195-smi-common-vpp          ?                      û                                Êapb smi gals0 gals1            /              y      larb@14013000             mediatek,mt8195-smi-larb            ?    0                z           m   z        û                    Êapb smi            /              }      iommu@14018000            mediatek,mt8195-iommu-vpp           ?    €              8  ‹   {   |   }   ~      €   �   ‚   ƒ   „   …   †   ‡   ˆ        ¨      R               û              Êbclk            é              /              x      clock-controller@14e00000             mediatek,mt8195-wpesys          ?    à                 î              !      clock-controller@14e02000             mediatek,mt8195-wpesys_vpp0         ?    à                 î         clock-controller@14e03000             mediatek,mt8195-wpesys_vpp1         ?    à0                î         larb@14e04000             mediatek,mt8195-smi-larb            ?    à@                z           m   ‰        û   !      !           Êapb smi            /              ž      larb@14e05000             mediatek,mt8195-smi-larb            ?    àP                z           m   y        û   !      !                 Êapb smi gals               /                    syscon@14f00000           mediatek,mt8195-vppsys1 syscon          ?    ð                 î           "   v   	                         mutex@14f01000            mediatek,mt8195-vpp-mutex           ?    ð                ¨      {               "   v   	              û       '           /         larb@14f02000             mediatek,mt8195-smi-larb            ?    ð                 z           m   ‰        û                            Êapb smi gals               /              �      larb@14f03000             mediatek,mt8195-smi-larb            ?    ð0                z           m   z        û                            Êapb smi gals               /              ~      display@14f06000              mediatek,mt8195-mdp3-split          ?    ð`                "   v   	  `            û              +       ,           /         display@14f07000              mediatek,mt8195-mdp3-tcc            ?    ðp                "   v   	  p            û             dma-controller@14f08000           mediatek,mt8195-mdp3-rdma           ?    ð€                "   v   	  €            :  „  ¨        û               [   Š               /           b         dma-controller@14f09000           mediatek,mt8195-mdp3-rdma           ?    ð�                "   v   	  �            :  …  ©        û       
        [   Š   ¤           /           b         dma-controller@14f0a000           mediatek,mt8195-mdp3-rdma           ?    ð                 "   v   	               :  †  ª        û               [   x   À           /           b         display@14f0b000              mediatek,mt8195-mdp3-fg         ?    ð°                "   v   	  °            û       	      display@14f0c000              mediatek,mt8195-mdp3-fg         ?    ðÀ                "   v   	  À            û             display@14f0d000              mediatek,mt8195-mdp3-fg         ?    ðÐ                "   v   	  Ð            û             display@14f0e000              mediatek,mt8195-mdp3-hdr            ?    ðà                "   v   	  à            û             display@14f0f000              mediatek,mt8195-mdp3-hdr            ?    ðð                "   v   	  ð            û             display@14f10000              mediatek,mt8195-mdp3-hdr            ?    ñ                 "   v   
               û              display@14f11000              mediatek,mt8195-mdp3-aal            ?    ñ                ¨      i               "   v   
              û                  /         display@14f12000              mediatek,mt8195-mdp3-aal            ?    ñ                 ¨      j               "   v   
               û                  /         display@14f13000              mediatek,mt8195-mdp3-aal            ?    ñ0                ¨      k               "   v   
  0            û       !           /         display@14f14000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    ñ@                "   v   
  @            :  �  ¯        û             display@14f15000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    ñP                "   v   
  P            :  ‘  °        û       $      display@14f16000          2    mediatek,mt8195-mdp3-rsz mediatek,mt8183-mdp3-rsz           ?    ñ`                "   v   
  `            :  ’  ±        û       %      display@14f17000              mediatek,mt8195-mdp3-tdshp          ?    ñp                "   v   
  p            û             display@14f18000              mediatek,mt8195-mdp3-tdshp          ?    ñ€                "   v   
  €            û       (      display@14f19000              mediatek,mt8195-mdp3-tdshp          ?    ñ�                "   v   
  �            û       )      display@14f1a000              mediatek,mt8195-mdp3-merge          ?    ñ                 "   v   
               û                  /         display@14f1b000              mediatek,mt8195-mdp3-merge          ?    ñ°                "   v   
  °            û                  /         display@14f1c000              mediatek,mt8195-mdp3-color          ?    ñÀ                ¨      t               "   v   
  À            û                  /         display@14f1d000              mediatek,mt8195-mdp3-color          ?    ñÐ                "   v   
  Ð            ¨      u               û                  /         display@14f1e000              mediatek,mt8195-mdp3-color          ?    ñà                ¨      v               "   v   
  à            û                  /         display@14f1f000              mediatek,mt8195-mdp3-ovl            ?    ñð                ¨      w               "   v   
  ð            û                   /           [   Š   ¢      display@14f20000              mediatek,mt8195-mdp3-padding            ?    ò                 "   v                  û                  /         display@14f21000              mediatek,mt8195-mdp3-padding            ?    ò                "   v                 û                  /         display@14f22000              mediatek,mt8195-mdp3-padding            ?    ò                 "   v                  û                  /         dma-controller@14f23000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    ò0                "   v     0            :  Ÿ  «        û               [   Š   £           /           b         dma-controller@14f24000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    ò@                "   v     @            :     ¬        û               [   Š   ¦           /           b         dma-controller@14f25000       4    mediatek,mt8195-mdp3-wrot mediatek,mt8183-mdp3-wrot         ?    òP                "   v     P            :  ¡  ­        û               [   x   Â           /           b         clock-controller@15000000             mediatek,mt8195-imgsys          ?                      î              (      larb@15001000             mediatek,mt8195-smi-larb            ?                     z   	        m   ‹        û   (       (       (   
        Êapb smi gals               /              Ÿ      smi@15002000              mediatek,mt8195-smi-sub-common          ?                      û   (      (                 Êapb smi gals0           m   y           /              Ž      smi@15003000              mediatek,mt8195-smi-sub-common          ?     0                û   (       (       (   
        Êapb smi gals0           m   ‰           /              ‹      clock-controller@15110000              mediatek,mt8195-imgsys1_dip_top         ?                     î              Œ      larb@15120000             mediatek,mt8195-smi-larb            ?                     z   
        m   ‹        û   (      Œ            Êapb smi            /                     clock-controller@15130000             mediatek,mt8195-imgsys1_dip_nr          ?                     î         clock-controller@15220000             mediatek,mt8195-imgsys1_wpe         ?    "                 î              �      larb@15230000             mediatek,mt8195-smi-larb            ?    #                 z           m   ‹        û   (      �            Êapb smi            /              ¡      clock-controller@15330000             mediatek,mt8195-ipesys          ?    3                 î              )      larb@15340000             mediatek,mt8195-smi-larb            ?    4                 z           m   Ž        û   )      )           Êapb smi            /              €      clock-controller@16000000             mediatek,mt8195-camsys          ?                      î              *      larb@16001000             mediatek,mt8195-smi-larb            ?                     z           m   �        û   *       *       *           Êapb smi gals               /              ¢      larb@16002000             mediatek,mt8195-smi-larb            ?                      z           m   �        û   *      *           Êapb smi            /              �      smi@16004000              mediatek,mt8195-smi-sub-common          ?     @                û   *       *       *           Êapb smi gals0           m   ‰           /              �      smi@16005000              mediatek,mt8195-smi-sub-common          ?     P                û   *      *                 Êapb smi gals0           m   y           /              �      larb@16012000             mediatek,mt8195-smi-larb            ?                     z           m   �        û   ‘       ‘            Êapb smi            /               ‚      larb@16013000             mediatek,mt8195-smi-larb            ?    0                z           m   �        û   ’       ’            Êapb smi            /               £      larb@16014000             mediatek,mt8195-smi-larb            ?    @                z           m   �        û   “       “            Êapb smi            /   !           ˆ      larb@16015000             mediatek,mt8195-smi-larb            ?    P                z           m   �        û   ”       ”            Êapb smi            /   !           ¨      clock-controller@1604f000             mediatek,mt8195-camsys_rawa         ?    ð                î              ‘      clock-controller@1606f000             mediatek,mt8195-camsys_yuva         ?    ð                î              ’      clock-controller@1608f000             mediatek,mt8195-camsys_rawb         ?    ð                î              “      clock-controller@160af000             mediatek,mt8195-camsys_yuvb         ?    
ð                î              ”      clock-controller@16140000             mediatek,mt8195-camsys_mraw         ?                     î              •      larb@16141000             mediatek,mt8195-smi-larb            ?                    z           m   �        û   *       •       *           Êapb smi gals               /   "           §      larb@16142000             mediatek,mt8195-smi-larb            ?                     z           m   �        û   •       •            Êapb smi            /   "           ‡      clock-controller@17200000             mediatek,mt8195-ccusys          ?                      î              –      larb@17201000             mediatek,mt8195-smi-larb            ?                     z           m   �        û   –       –            Êapb smi            /              ƒ      video-codec@18000000              mediatek,mt8195-vcodec-dec          N   w        [   Š                        +            ?                   @                d                    `    video-codec@2000              mediatek,mtk-vcodec-lat-soc         ?                       [   x  à   x  á         û      A   "      "         �        Êsel vdec lat top                   A              �           /         video-codec@10000             mediatek,mtk-vcodec-lat         ?                      ¨      Ä             0  [   Š      Š     Š     Š     Š     Š           û      A   "      "         �        Êsel vdec lat top                   A              �           /         video-codec@25000             mediatek,mtk-vcodec-core            ?     P                ¨      Ã             P  [   Š      Š  ¡   Š  ¢   Š  £   Š  ¤   Š  ¥   Š  ¦   Š  §   Š  ¨   Š  ©         û      A   #      #         �        Êsel vdec lat top                   A              �           /            larb@1800d000             mediatek,mt8195-smi-larb            ?     Ð                z           m   ‰        û   "       "            Êapb smi            /              ¦      larb@1800e000             mediatek,mt8195-smi-larb            ?     à                z           m   —        û         "            Êapb smi            /              †      clock-controller@1800f000             mediatek,mt8195-vdecsys_soc         ?     ð                î              "      larb@1802e000             mediatek,mt8195-smi-larb            ?    à                z           m   ‰        û   #       #            Êapb smi            /              ¥      clock-controller@1802f000             mediatek,mt8195-vdecsys         ?    ð                î              #      larb@1803e000             mediatek,mt8195-smi-larb            ?    à                z           m   —        û         $            Êapb smi            /              …      clock-controller@1803f000             mediatek,mt8195-vdecsys_core1           ?    ð                î              $      clock-controller@190f3000             mediatek,mt8195-apusys_pll          ?    0                î         clock-controller@1a000000             mediatek,mt8195-vencsys         ?                      î              %      larb@1a010000             mediatek,mt8195-smi-larb            ?                     z           m   ‰        û   %      %           Êapb smi            /              ¤      video-codec@1a020000              mediatek,mt8195-vcodec-enc          ?                   H  [   Š  `   Š  a   Š  b   Š  c   Š  d   Š  v   Š  w   Š  x   Š  y        ¨      U               N   w        û   %         	  Êvenc_sel                   @              �           /                        +         jpgdec-master             mediatek,mt8195-jpgdec             /         0  [   Š  m   Š  n   Š  r   Š  s   Š  t   Š  u                     +            d   jpgdec@1a040000           mediatek,mt8195-jpgdec-hw           ?                   0  [   Š  m   Š  n   Š  r   Š  s   Š  t   Š  u        ¨      W               û   %           Êjpgdec             /         jpgdec@1a050000           mediatek,mt8195-jpgdec-hw           ?                   0  [   Š  m   Š  n   Š  r   Š  s   Š  t   Š  u        ¨      X               û   %           Êjpgdec             /         jpgdec@1b040000           mediatek,mt8195-jpgdec-hw           ?                   0  [   x  �   x  Ž   x  ’   x  “   x  ”   x  •        ¨      \               û   &           Êjpgdec             /            clock-controller@1b000000             mediatek,mt8195-vencsys_core1           ?                      î              &      syscon@1c01a000       5    mediatek,mt8195-vdosys0 mediatek,mt8195-mmsys syscon            ?                     )   ˜               î           "   ˜                           jpgenc-master             mediatek,mt8195-jpgenc             /            [   x  ‡   x  ˆ   x  ‰   x  Œ                     +            d   jpgenc@1a030000           mediatek,mt8195-jpgenc-hw           ?                      [   Š  g   Š  h   Š  i   Š  l        ¨      V               û   %           Êjpgenc             /         jpgenc@1b030000           mediatek,mt8195-jpgenc-hw           ?                      [   x  ‡   x  ˆ   x  ‰   x  Œ        ¨      [               û   &           Êjpgenc             /            larb@1b010000             mediatek,mt8195-smi-larb            ?                     z           m   y        û   &      &                  Êapb smi gals               /              „      ovl@1c000000              mediatek,mt8195-disp-ovl            ?                      ¨      |                  /           û               [   Š           "   ˜                rdma@1c002000             mediatek,mt8195-disp-rdma           ?                      ¨      ~                  /           û              [   Š            "   ˜                color@1c003000        6    mediatek,mt8195-disp-color mediatek,mt8173-disp-color           ?     0                ¨                        /           û              "   ˜     0          ccorr@1c004000        6    mediatek,mt8195-disp-ccorr mediatek,mt8192-disp-ccorr           ?     @                ¨      €                  /           û              "   ˜     @          aal@1c005000          2    mediatek,mt8195-disp-aal mediatek,mt8183-disp-aal           ?     P                ¨      �                  /           û              "   ˜     P          gamma@1c006000        6    mediatek,mt8195-disp-gamma mediatek,mt8183-disp-gamma           ?     `                ¨      ‚                  /           û              "   ˜     `          dither@1c007000       8    mediatek,mt8195-disp-dither mediatek,mt8183-disp-dither         ?     p                ¨      ƒ                  /           û      	        "   ˜     p          dsi@1c008000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         ?     €                ¨      „                  /           û            *   ™        Êengine digital hs           `   ™        	ÿdphy          	  ¸disabled          dsc@1c009000              mediatek,mt8195-disp-dsc            ?     �                ¨      …                  /           û              "   ˜     �          dsi@1c012000          (    mediatek,mt8195-dsi mediatek,mt8183-dsi         ?                     ¨      Ž                  /           û            +   š        Êengine digital hs           `   š        	ÿdphy          	  ¸disabled          merge@1c014000            mediatek,mt8195-disp-merge          ?    @                ¨      �                  /           û              "   ˜     @          dp-intf@1c015000              mediatek,mt8195-dp-intf         ?    P                ¨      ‘               û      ,                    Êpixel engine pll          	  ¸disabled          mutex@1c016000            mediatek,mt8195-disp-mutex          ?    `                ¨      ’                  /           û              "   ˜     `            :  U      larb@1c018000             mediatek,mt8195-smi-larb            ?    €                z            m   ‰        û      (      (              Êapb smi gals               /              ›      larb@1c019000             mediatek,mt8195-smi-larb            ?    �                z           m   y        û      (                     Êapb smi gals               /              {      syscon@1c100000           mediatek,mt8195-vdosys1 syscon          ?                     )   ˜              "   ˜                  î           ¼              '      smi@1c01b000              mediatek,mt8195-smi-common-vdo          ?    °                 û      %      &      )      $        Êapb smi gals0 gals1            /              ‰      iommu@1c01f000            mediatek,mt8195-iommu-vdo           ?    ð              8  ‹   ›   œ   �   ž   Ÿ       ¡   ¢   £   ¤   ¥   ¦   §   ¨        ¨      �               é           û      '        Êbclk               /              Š      mutex@1c101000            mediatek,mt8195-disp-mutex          ?                    ¨      î                  /           û   '           "   ˜                 :  À      larb@1c102000             mediatek,mt8195-smi-larb            ?                     z           m   ‰        û   '       '       '           Êapb smi gals               /              œ      larb@1c103000             mediatek,mt8195-smi-larb            ?    0                z           m   y        û   '      '                  Êapb smi gals               /              |      dma-controller@1c104000           mediatek,mt8195-vdo1-rdma           ?    @                ¨      ï               û   '              /           [   Š   @        "   ˜     @            b         dma-controller@1c105000           mediatek,mt8195-vdo1-rdma           ?    P                ¨      ð               û   '              /           [   x   `        "   ˜     P            b         dma-controller@1c106000           mediatek,mt8195-vdo1-rdma           ?    `                ¨      ñ               û   '              /           [   Š   A        "   ˜     `            b         dma-controller@1c107000           mediatek,mt8195-vdo1-rdma           ?    p                ¨      ò               û   '              /           [   x   a        "   ˜     p            b         dma-controller@1c108000           mediatek,mt8195-vdo1-rdma           ?    €                ¨      ó               û   '              /           [   Š   B        "   ˜     €            b         dma-controller@1c109000           mediatek,mt8195-vdo1-rdma           ?    �                ¨      ô               û   '              /           [   x   b        "   ˜     �            b         dma-controller@1c10a000           mediatek,mt8195-vdo1-rdma           ?                     ¨      õ               û   '              /           [   Š   C        "   ˜                  b         dma-controller@1c10b000           mediatek,mt8195-vdo1-rdma           ?    °                ¨      ö               û   '              /           [   x   c        "   ˜     °            b         vpp-merge@1c10c000            mediatek,mt8195-disp-merge          ?    À                ¨      ÷               û   '   	   '           Êmerge merge_async              /           "   ˜     À             š        B   '         vpp-merge@1c10d000            mediatek,mt8195-disp-merge          ?    Ð                ¨      ø               û   '   
   '           Êmerge merge_async              /           "   ˜     Ð             š        B   '         vpp-merge@1c10e000            mediatek,mt8195-disp-merge          ?    à                ¨      ù               û   '      '           Êmerge merge_async              /           "   ˜     à             š        B   '         vpp-merge@1c10f000            mediatek,mt8195-disp-merge          ?    ð                ¨      ú               û   '      '           Êmerge merge_async              /           "   ˜     ð             š        B   '         vpp-merge@1c110000            mediatek,mt8195-disp-merge          ?                     ¨      û               û   '      '           Êmerge merge_async              /           "   ˜                   ®        B   '         dp-intf@1c113000              mediatek,mt8195-dp-intf         ?    0                ¨                        /           û   '   /   '                 Êpixel engine pll          	  ¸disabled          hdr-engine@1c114000           mediatek,mt8195-disp-ethdr        p  ?    @            P            p            �                         °            À              4  Émixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds       p  "   ˜     @       ˜     P       ˜     p       ˜     �       ˜             ˜     °       ˜     À          h  û   '   %   '       '   #   '   !   '   $   '   "   '   1   '   &   '   '   '   (   '   )   '   *            ƒ  Êmixer vdo_fe0 vdo_fe1 gfx_fe0 gfx_fe1 vdo_be adl_ds vdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async ethdr_top             /           [   x   d   x   e        ¨                   (  B   '   3   '   4   '   5   '   6   '   7      E  Ivdo_fe0_async vdo_fe1_async gfx_fe0_async gfx_fe1_async vdo_be_async          edp-tx@1c500000           mediatek,mt8195-edp-tx          ?    P        €         m   ©        ydp_calibration_data            /           ¨      ¤               Å  ¤      	  ¸disabled          dp-tx@1c600000            mediatek,mt8195-dp-tx           ?    `        €         m   ©        ydp_calibration_data            /           ¨      Ê               Å  ¤      	  ¸disabled             thermal-zones      cpu0-thermal            Ö  è        ä   ú        ú   ª      trips      trip-alert          
 L          Ð         Epassive            «      trip-crit           
 †           Ð      	   Ecritical             cooling-maps       map0            !   «      0  &   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu1-thermal            Ö  è        ä   ú        ú   ª      trips      trip-alert          
 L          Ð         Epassive            ¬      trip-crit           
 †           Ð      	   Ecritical             cooling-maps       map0            !   ¬      0  &   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu2-thermal            Ö  è        ä   ú        ú   ª      trips      trip-alert          
 L          Ð         Epassive            ­      trip-crit           
 †           Ð      	   Ecritical             cooling-maps       map0            !   ­      0  &   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu3-thermal            Ö  è        ä   ú        ú   ª      trips      trip-alert          
 L          Ð         Epassive            ®      trip-crit           
 †           Ð      	   Ecritical             cooling-maps       map0            !   ®      0  &   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu4-thermal            Ö  è        ä   ú        ú   ª       trips      trip-alert          
 L          Ð         Epassive            ¯      trip-crit           
 †           Ð      	   Ecritical             cooling-maps       map0            !   ¯      0  &   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu5-thermal            Ö  è        ä   ú        ú   ª      trips      trip-alert          
 L          Ð         Epassive            °      trip-crit           
 †           Ð      	   Ecritical             cooling-maps       map0            !   °      0  &   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu6-thermal            Ö  è        ä   ú        ú   ª      trips      trip-alert          
 L          Ð         Epassive            ±      trip-crit           
 †           Ð      	   Ecritical             cooling-maps       map0            !   ±      0  &   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            cpu7-thermal            Ö  è        ä   ú        ú   ª      trips      trip-alert          
 L          Ð         Epassive            ²      trip-crit           
 †           Ð      	   Ecritical             cooling-maps       map0            !   ²      0  &   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ   ÿÿÿÿÿÿÿÿ            vpu0-thermal            Ö  è        ä   ú        ú   ³      trips      trip-alert          
 L          Ð         Epassive       trip-crit           
 †           Ð      	   Ecritical                vpu1-thermal            Ö  è        ä   ú        ú   ³   	   trips      trip-alert          
 L          Ð         Epassive       trip-crit           
 †           Ð      	   Ecritical                gpu-thermal         Ö  è        ä   ú        ú   ³   
   trips      trip-alert          
 L          Ð         Epassive       trip-crit           
 †           Ð      	   Ecritical                gpu1-thermal            Ö  è        ä   ú        ú   ³      trips      trip-alert          
 L          Ð         Epassive       trip-crit           
 †           Ð      	   Ecritical                vdec-thermal            Ö  è        ä   ú        ú   ³      trips      trip-alert          
 L          Ð         Epassive       trip-crit           
 †           Ð      	   Ecritical                img-thermal         Ö  è        ä   ú        ú   ³      trips      trip-alert          
 L          Ð         Epassive       trip-crit           
 †           Ð      	   Ecritical                infra-thermal           Ö  è        ä   ú        ú   ³      trips      trip-alert          
 L          Ð         Epassive       trip-crit           
 †           Ð      	   Ecritical                cam0-thermal            Ö  è        ä   ú        ú   ³      trips      trip-alert          
 L          Ð         Epassive       trip-crit           
 †           Ð      	   Ecritical                cam1-thermal            Ö  è        ä   ú        ú   ³      trips      trip-alert          
 L          Ð         Epassive       trip-crit           
 †           Ð      	   Ecritical                   chosen          5serial0:921600n8          firmware       optee             linaro,optee-tz         Jsmc          memory@40000000         3memory          ?    @                regulator-wifi-3v3-en             regulator-fixed         Mwifi_3v3_en          ¨        \ 2Z         t 2Z          A        ˆ      C            _default         U   ´        T   P      regulator-vsys            regulator-fixed         Mvsys             ¨         _        \ LK@        t LK@        T   µ           P      regulator-vsys-buck           regulator-fixed       
  Mvsys_buck            ¨         _        \ LK@        t LK@        T   µ           ^      regulator-vcc5v0-sys              regulator-fixed         Mvcc5v0_sys           ¨         _           µ      reserved-memory                      +            d   optee@43200000          ?    C        À           q      memory@50000000           shared-dma-pool         ?    P       �           q           -      memory@53000000           shared-dma-pool         ?    S       @        memory@54600000         ?    T`                   q      memory@60000000           shared-dma-pool         ?    `                  q      memory@62000000           shared-dma-pool         ?    b       @              	compatible interrupt-parent #address-cells #size-cells model chassis-type dp-intf0 dp-intf1 gce0 gce1 ethdr0 mutex0 mutex1 merge1 merge2 merge3 merge4 merge5 vdo1-rdma0 vdo1-rdma1 vdo1-rdma2 vdo1-rdma3 vdo1-rdma4 vdo1-rdma5 vdo1-rdma6 vdo1-rdma7 i2c0 i2c1 i2c2 i2c3 i2c4 ethernet0 serial0 serial1 spi0 spi1 device_type reg enable-method performance-domains clock-frequency capacity-dmips-mhz cpu-idle-states i-cache-size i-cache-line-size i-cache-sets d-cache-size d-cache-line-size d-cache-sets next-level-cache #cooling-cells cpu-supply phandle cpu entry-method arm,psci-suspend-param local-timer-stop entry-latency-us exit-latency-us min-residency-us cache-level cache-unified interrupts cpus status num-channels wakeup-delay-ms mediatek,platform #clock-cells clocks clock-div clock-mult clock-output-names #performance-domain-cells opp-shared opp-hz opp-microvolt ranges dma-ranges #interrupt-cells #redistributor-regions interrupt-controller affinity #reset-cells reg-names gpio-controller #gpio-cells gpio-ranges mediatek,rsel-resistance-in-si-unit pinmux drive-strength input-enable output-high bias-disable input-disable bias-pull-up drive-strength-microamp bias-pull-down output-low #power-domain-cells domain-supply clock-names mediatek,infracfg mediatek,disable-extrst assigned-clocks assigned-clock-parents interrupts-extended #io-channel-cells regulator-name regulator-min-microvolt regulator-max-microvolt regulator-enable-ramp-delay regulator-always-on regulator-ramp-delay regulator-allowed-modes #iommu-cells #mbox-cells memory-region power-domains mbox-names mboxes mediatek,topckgen resets reset-names pinctrl-0 pinctrl-names nvmem-cells nvmem-cell-names #thermal-sensor-cells #pwm-cells mediatek,pad-select interrupt-names mediatek,pericfg snps,axi-config snps,mtl-rx-config snps,mtl-tx-config snps,txpbl snps,rxpbl snps,clk-csr phy-mode phy-handle pinctrl-1 mediatek,tx-delay-ps mediatek,mac-wol snps,reset-gpio snps,reset-delays-us snps,wr_osr_lmt snps,rd_osr_lmt snps,blen snps,rx-queues-to-use snps,rx-sched-sp snps,dcb-algorithm snps,map-to-dma-channel snps,tx-queues-to-use snps,tx-sched-wrr snps,weight snps,priority phys wakeup-source mediatek,syscon-wakeup role-switch-default-mode usb-role-switch vusb33-supply vbus-supply remote-endpoint bus-width max-frequency hs400-ds-delay cap-mmc-highspeed cap-mmc-hw-reset mmc-hs200-1_8v mmc-hs400-1_8v no-sdio no-sd non-removable vmmc-supply vqmmc-supply cap-sd-highspeed cd-gpios no-mmc sd-uhs-sdr50 sd-uhs-sdr104 usb2-lpm-disable mediatek,u3p-dis-msk bus-range iommu-map iommu-map-mask phy-names interrupt-map-mask interrupt-map bits #phy-cells richtek,vinovp-microvolt LDO_VIN1-supply LDO_VIN3-supply label data-role op-sink-microwatt power-role try-power-role source-pdos sink-pdos mode-switch orientation-switch vcc-supply operating-points-v2 power-domain-names mali-supply mediatek,gce-client-reg mediatek,gce-events mediatek,scp iommus #dma-cells mediatek,smi mediatek,larb-id mediatek,larbs mediatek,merge-mute mediatek,merge-fifo-en max-linkrate-mhz polling-delay polling-delay-passive thermal-sensors temperature hysteresis trip cooling-device stdout-path enable-active-high vin-supply regulator-boot-on no-map 